i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs

Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.

Also, update the BSpec quote that discusses the workaround to reflect
the latest BSpec.

The BSpec states that the workaround is required for Ivybridge and
Baytrail as well as Haswell. But, we apply the workaround to only
Haswell because (a) we suspect that is the only hardware where it is
actually required and (b) we haven't yet validated the workaround for
the other hardware.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
OTC-Tracker: CHRMOS-812
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
clover: Fix missing minus sign in 'iterator_adaptor::operator-='.

The method is currently unused, this probably doesn't fix anything at
this point.
i965/vs: Don't copy propagate into SEND-from-GRF messages.

SEND can't deal with swizzles, source modifiers, and so on.  This should
avoid problems with VS pull constant loads on Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965/vs: Always store pull constant offsets in GRFs on Gen8.

We need to SEND from a GRF, and we can only obtain those prior to
register allocation.

This allows us to do pull constant loads without the MRF hack.

v2: Reword comments (suggested by Paul).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965: Set vertical alignment unit to 4 on Broadwell.

Broadwell doesn't support a surface vertical alignment of 2.  It only
supports VALIGN_4, VALIGN_8, or VALIGN_16.  I chose 4 since it's the
least wasteful.

v2: Replace my comment with a better one from Eric.  Move Broadwell
    checks earlier so it's more obvious that "return 2" won't be hit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Fix texture swizzling on Broadwell.

Like Haswell, we do this in SURFACE_STATE rather than shader
workarounds.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Don't use MACH for integer multiplies on Gen8+.

The documentation is really hard to follow, but apparently a 32-bit x
32-bit multiply just works without the MACH macro.  The macro apparently
is only necessary to get the full 64-bit value.

Fixes Piglit tests [vf]s-op-mult-int-int.shader_test.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Fix texture border color on Broadwell.

The Gen7 sampler state code still works.  Increasing the alignment to
64 bytes makes bit 5 zero, which is good because it's now reserved.

Since we don't use the new filter bits, we can leave those as zero too,
which means we don't need to update the code to update the pointer.
(We probably should anyway, for clarity, but alas, another day.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Skip the register write check on Broadwell.

MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work.  But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
freedreno: Add a few texture formats
egl: add HAVE_LIBDRM define, fix EGL X11 platform

Commit a594cec broke EGL X11 backend by adding dependency between
X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11.

This patch fixes the issue by adding additional define for libdrm
detection independent of which backend is being compiled. Tested by
compiling Mesa with '--with-egl-platforms=x11' and running es2gears_x11
+ glbenchmark2.7 successfully.

v2: return true for dri2_auth if running without libdrm (Samuel)
v3: check libdrm when building EGL drm platform + AM_CFLAGS fix (Emil)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72062
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Cc: Samuel Thibault <samuel.thibault@ens-lyon.org>
Cc: mesa-stable@lists.freedesktop.org
i965/gen7: Apply non-msrt fast color clear w/a to all gen7

The BSpec states that for IVB, VLVT, and HSW, the aligment for the
non-msrt clear rectangle must be doubled.  Commit 9a1a67b applied the
workaround to Haswell GT3.  Commit 8b659ce expanded the workaround to
all Haswell variants. This commit expands it to all Gen7 hardware, as
required by the BSpec.

No Piglit regressions on Ivybridge 0x0166. No fixes either.

I know no Ivybridge nor Baytrail bug related to this workaround.
However, the BSpec says the extra alignment is required, so let's do it.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
CC: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>