Fix MCCodeEmitter to emit the instructions correctly
The Function alignment was because of MCCodeEmitter emitting wrong
number of bytes. That bug was fixed by previous commit so removing
this workaround.
Use rD, rS1, rS2 and imm16 to be consistent with TeeRISC CPU
Specification.

This change makes easy to review how the tblgen maps the operand
specified in the .td files to Instruction class.

See the following link for more information about tblgen mapping
http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-operand-mapping
Fix some coding style and variable naming.
Add disassembler support.

The following command now disassembles simple file
llvm-objdump -arch=teerisc -d test.s.o