OMAP4: DPLL cascading: Introduce menuconfig option

New menuconfig option CONFIG_OMAP4_DPLL_CASCADING will be
used for DPLL cascading feature. All related code should
use it.

Change-Id: I221d1bf92419cc84fdd014b0d20f49f18691d3b1
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: introduce DPLL cascading blocker API

Some devices cannot operate correctly while in DPLL cacading mode used
for low power MP3 playback.  Thus two new functions have been created which
can be used by device drivers to block entry, exit and allow entry into DPLL
cascading.

Function protoypes are:

int omap4_dpll_cascading_blocker_hold(struct device *dev);
int omap4_dpll_cascading_blocker_release(struct device *dev);

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: I6df901c2790d874166ac5c4231cedd8c9b18d170
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: Clock: new DPLL_CORE set_rate, and M2 fixes

omap4_dpll_dpll_set_rate checks for target rate matching the clk_bypass rate
and enters Low Power Bypass in that case. Otherwise it rounds the rate and
locks the DPLL at the new rate.  Same function handles EMIF programming.

omap4_dpll_core_m2_set_rate now has better documentation, follows the same
coding style as the above function and is a bit safer by forcing clk_enable
and clk_disable calls on emif1_fck and emif2_fck.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: I921be9d20fe9e9c5b5604dceb4e5aa037a6b7009
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: ASoC: ABE DSP: DPLL cascading: Add initial support

DPLL cascading mode can be entered when the following conditions
are met:
 - System is in early suspend (screen is off)
 - Multimedia Low-Power port is active (ping-pong)
 - OPP is 50 or less (DL1 path only)

ABE DSP driver will leave DPLL cascading mode when:
 - Screen is on
 - Any other port apart from Multimedia Low-Power is used
 - Stream is closed

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Ib239730806e44456f45611c6eca1150733635470
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: applying hold/release API to serial driver

Serial driver can block DPLL cascading only form non-atomic
context, if any external device uses UART.

Change-Id: I56d31a296b8a644cb2cf066b4aa7b22d2c07027a
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: usage of DPLL cascading blocker API on HSI activity

When HSI driver is probed, it sets a constraint to keep HSI Fclk at 96 MHz.
But this constraint was not released, thus it was not possible to enter
OPPLP (used for DPLL cascading).

Now DPLL cascading blocker constraint is set and release based on HSI
activity.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Id8ace8f8a4f0a24641e51023346a745ecaaaf423
Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL csacading: CPUfreq: manage DPLL cascading constraint

Only release a DPLL cascading constraint when at the lowest OPP,
otherwise hold a constraint blocking DPLL cascading entry.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Ic842773e7a20bb2250cfd44c674a531d9fbec46f
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: MUSB core: USB handling during DPLL casacading

System can enter DPLL cascading mode only when USB is unplugged.
When USB is plugged, system left DPLL cascading

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: I83c887a278f48962446a3b17ec0d60f853506f90
Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: The HSMMC output clock handling to support DPLL cascading

The HSMMC1 output clock will change from 96MHz to 49MHz upon entry
to DPLL cascading mode. This patch modifies the MMC1 divisor to
handle the change in clock frequency.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Ia52425132bfcc80489b39cb5562dc86cc483cb83
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: Recalibrate Baud Rates for UARTs when the DPLL freq changes

This patch attached the callbacks to DPLL framework to recalib.
the baud rates of all the UART's base on the functional clock
chnages in the DPLL cascading Low Power mode.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: If60b3287934f8d780b72b3aa68cbeccd52f99658
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: I2C psc reconfiguration to support DPLL cascading

The I2C clocks change from 96MHz to 48MHz in dpll cascading
mode.The I2C driver is registerd with DPLL cascading and
the change in clocks is handled.The device speed of > 1Mbps
is not supported in DPLL cascading mode.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Ib37648012476a8246cc9e437f707b6e3969e13a3
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>

Conflicts:

	drivers/i2c/busses/i2c-omap.c
OMAP4: DPLL cascading: SR: handle SRCLKLENGTH

In DPLL cascading mode SYS_CLK is gated.  This impacts many IP, including
the SmartReflex AVS modules.  To compensate for loss of SYS_CLK the
SR_xxx_SYSCLK clocks derived from the PRM use the 32K timer as a clock
source.  As such the SRCLKLENGTH value needs to be updated for this
change in frequency.  In DPLL cascading the rate of this clock should be
12.288MHz.

This patch implements three distinct changes:

1) add a 12.288MHz option to the existing sr_set_clk_length function
and give it the ability to detect whether we are in DPLL cascading
mode or not.
2) Remove optimizations in sr_configure_errgen and sr_configure_minmax to
skip sr_set_clk_length re-calibration if the clk_length parameter exists.
The assumption was that this value would never change after initial
calibration at boot; that assumption fails in light of DPLL cascading
scenario.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Ie657459e53838067139a4dd7316a6adc1f5e7259
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: mute warnings during DPLL cascading

1) PM: mute warn from min_bus_tput constraint

When the omap_device_set_rate function is called from
omap_pm_set_min_bus_tput and fails, a warn is printed.  This behavior is
normal and expected in DPLL cascading mode, so the warn has been
converted to pr_debug to minimize console noise.

2)clock: mute WARN when searching for fieldval

This warn is hit every time when entering DPLL cascading.  This is due
to a workaround implemented in DPLL cascading code which must circumvent the
clock framework to change l4_wkup_iclk's parent from SYS_CK to
DPLL_ABE's LP output, and back again.
During low power MP3 playback it is observed that this warn can disrupt
playback by causing a rapid exit/re-entry of the DPLL cascading mode.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: Id040a4710303845ebc9eeca81c1c06d49f922230
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: hold DPLL cascading constraint before warm reset

System has to be out of DPLL cascading while warm reset is initiated.
Hold DPLL cascading constraint to prevent entering to cascading state.

Change-Id: I30d9bd9fffe3c545fd89ec6f677039a4028e89e6
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: introduce DPLL_ABE low power bypass/cascade

DPLL_ABE can output 196.608MHz when fed from the 32KHz timer if
CM_CLKMODE_DPLL_ABE.REGM4XEN is set.  This unique property allows us to
make DPLL_ABE the parent of DPLL_CORE and then drive DPLL_MPU and DPLL_IVA,
all of which are in Low Power Bypass mode.  This allows the system to remain
usable while consuming far less power than when all of the DPLLs are
locked. The primary use case for this mode low power audio playback with the
display turned off.

Many caveats exist in this DPLL cascading mode:
DSS operation is unsupported, MPU is limited to 196.608MHz, ABE runs at
49.152MHz in LP mode and there are no doubt others we haven't figured
out yet.

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: I63ce263dd793801b9b13daff4d1b5f8f326b6d98
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: introduce devise scale function for GPU

GPU driver should be able to manage DPLL cascading constraint.
Right now sources of GPU driver are not in the kernel mainline.
So, patch introduces simple wrapper function for omap_device_scale(),
which holds DPLL cascading blocker when GPU scales to OPP higher, than
OPP50

Change-Id: I3f83b8b1c49118625f550aea031e86546ceb97fc
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: Tune cpufreq interactive governor

During DPLL cascading timer_rate of interactive timer should be
increased, otherwise interactive governor will try to put system
out of DPLL cascading very frequently

[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]

Change-Id: I99bd86a8277b75f3f985124372f1c1b02f7d5ff2
Signed-off-by: Nicole Chalhoub <n-chalhoub@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
OMAP4: DPLL cascading: Add option which allows using DPLL cascading only for OMAP4430

Current DPLL cascading implementation is going to be used only on OMAP4430.
This patch adds config option to enable DPLL cascading only for OMAP4430.

Change-Id: I4942cef5ada3c7b764876fb44bfa9fb02e3e9730
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>