Remove unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179530 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid outputting temporary test file into source tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179532 91177308-0d34-0410-b5e6-96231b3b80d8
Remove getters now that we can specialize structs on the host endianness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179534 91177308-0d34-0410-b5e6-96231b3b80d8
Fix bit size of v64i8 and v32i16 vector types.

Patch by Cameron McInally <cameron.mcinally@nyu.edu>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179535 91177308-0d34-0410-b5e6-96231b3b80d8
Try to fix the mingw builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179536 91177308-0d34-0410-b5e6-96231b3b80d8
Grammar and punctuation fixes.
No content changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179540 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify the MCInst operator iterator declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179541 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179542 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Emit ELF formatted code rather than raw ISA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Emit configuration value in the .AMDGPU.config ELF section

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Emit config values in register value pairs.

Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
Fix endianness on some MSVC versions.

Looks like it was evaluating undef == undef to true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179549 91177308-0d34-0410-b5e6-96231b3b80d8
Fix silly typo that broke big endian hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179551 91177308-0d34-0410-b5e6-96231b3b80d8
SLPVectorizer: Make it a function pass and add code for hoisting the vector-gather sequence out of loops.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179562 91177308-0d34-0410-b5e6-96231b3b80d8
Update the release notes about the vectorizers.

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Fix the internal link.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179565 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a grammar mistake, and add a line about the two phases that the BB/SLP vectorizers have (top-down and bottom-up). 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179566 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: Explicit floating point condition register recognition.

This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
We are not able to bitcast a pointer to an integral value.

Two return types are not equivalent if one is a pointer and the other is an
integral. This is because we cannot bitcast a pointer to an integral value.
PR15185


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179569 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Add VACLT and VACLE assembly aliases.

These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.

rdar://13638090

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