Add support for passing -main-file-name all the way through to
the assembler.

Part of PR14624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170390 91177308-0d34-0410-b5e6-96231b3b80d8
Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170394 91177308-0d34-0410-b5e6-96231b3b80d8
Repair bundles that were broken by removing and reinserting the first
instruction.

This isn't strictly necessary at the moment because Thumb2SizeReduction
also copies all MI flags from the old instruction to the new. However, a
future patch will make that kind of direct flag tampering illegal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170395 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup comment and formatting


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170398 91177308-0d34-0410-b5e6-96231b3b80d8
Initialize NoRedZone and remove unused default values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170404 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/MC/ELF/comp-dir.s: Appease MSYS Bash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170410 91177308-0d34-0410-b5e6-96231b3b80d8
SROA: Replace calls to getScalarSizeInBits to DataLayout's API because
getScalarSizeInBits could not handle vectors of pointers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170412 91177308-0d34-0410-b5e6-96231b3b80d8
Rename the test so that we can add additional vectors-of-pointers tests
into the same file in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170414 91177308-0d34-0410-b5e6-96231b3b80d8
Enable the loop vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170416 91177308-0d34-0410-b5e6-96231b3b80d8
Check multiple register classes for inline asm tied registers

A register can be associated with several distinct register classes.
For example, on PPC, the floating point registers are each associated with
both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code
would fail when provided with a floating point register and an f64 operand
because it would happen to find the register in the F4RC class first and
return that. From the F4RC class, SDAG would extract f32 as the register
type and then assert because of the invalid implied conversion between
the f64 value and the f32 register.

Instead, search all register classes. If a register class containing the
the requested register has the requested type, then return that register
class. Otherwise, as before, return the first register class found that
contains the requested register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170436 91177308-0d34-0410-b5e6-96231b3b80d8
Tighten the insert() API for bundled instructions.

The normal insert() function takes an MBB::iterator position, and
inserts a stand-alone MachineInstr as before.

The insert() function that takes an MBB::instr_iterator position can
insert instructions inside a bundle, and will now update the bundle
flags correctly when that happens.

When the insert position is between two bundles, it is unclear whether
the instruction should be appended to the previous bundle, prepended to
the next bundle, or stand on its own. The MBB::insert() function doesn't
bundle the instruction in that case, use the MIBundleBuilder class for
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170437 91177308-0d34-0410-b5e6-96231b3b80d8
Get rid of the pesky -Woverloaded-virtual warning. No change in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170438 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorize: Emit reductions as log2(vectorsize) shuffles + vector ops instead of scalar operations.

For example on x86 with SSE4.2 a <8 x i8> add reduction becomes
	movdqa	%xmm0, %xmm1
	movhlps	%xmm1, %xmm1            ## xmm1 = xmm1[1,1]
	paddw	%xmm0, %xmm1
	pshufd	$1, %xmm1, %xmm0        ## xmm0 = xmm1[1,0,0,0]
	paddw	%xmm1, %xmm0
	phaddw	%xmm0, %xmm0
	pextrb	$0, %xmm0, %edx

instead of
	pextrb	$2, %xmm0, %esi
	pextrb	$0, %xmm0, %edx
	addb	%sil, %dl
	pextrb	$4, %xmm0, %esi
	addb	%dl, %sil
	pextrb	$6, %xmm0, %edx
	addb	%sil, %dl
	pextrb	$8, %xmm0, %esi
	addb	%dl, %sil
	pextrb	$10, %xmm0, %edi
	pextrb	$14, %xmm0, %edx
	addb	%sil, %dil
	pextrb	$12, %xmm0, %esi
	addb	%dil, %sil
	addb	%sil, %dl

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170439 91177308-0d34-0410-b5e6-96231b3b80d8
Add an assertion for a likely ilist::splice() contract violation.

The single-element ilist::splice() function supports a noop move:

  List.splice(I, List, I);

The corresponding std::list function doesn't allow that, so add a unit
test to document that behavior.

This also means that

  List.splice(I, List, F);

is somewhat surprisingly not equivalent to

  List.splice(I, List, F, next(F));

This patch adds an assertion to catch the illegal case I == F above.
Alternatively, we could make I == F a legal noop, but that would make
ilist differ even more from std::list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170443 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: minor improvement, initialize remaining resources before the first scheduling decision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170449 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: cleanup, use the proper iterator type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170450 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170451 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: Heuristics, compare latency more precisely. It matters more for some targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170452 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: Cleanup, redundant statement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170453 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: add dependence to ExitSU to model live-out latency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170454 91177308-0d34-0410-b5e6-96231b3b80d8