Mend some formulas (check this work) and simplify
Translate process working again

Mended some warnings from ISE, things that Icarus accepted but which
were not correct. Mended clock buffer.
Update clock block to stop generating phased clocks
Map process works again.

Remove constraints for obsolete clocks.
Data clock is not inverted from normal clock (needs testing).
Mend synthesis issues with clocks

Bitstream runs on hardware again.
Rename clocks
Remove intermediate assembly file

Use ../verilog/fib.tas.cpp for small.coe (and remember to copy it into
ipcore_dir).