ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.

These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093

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Merge these 2 tests in a single file.

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Unify and clean up.

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R600: Remove fmul.v4f32.ll test which is redundant with fmul.ll

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R600: Use SchedModel enum for is{Trans,Vector}Only functions

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R600: Non vector only instruction can be scheduled on trans unit

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R600: Use shared op optimization when checking cycle compatibility

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Rename some variables to match the style guide.

I am about to patch this code, and this makes the diff far more readable.

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Change swift/vldm test case to be less dependent on allocation order

'Force' values in registers using the calling convention. Now, we only depend on
the calling convention and that the allocator performs copy coalescing.

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Added -misched-regpressure option.

Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

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mi-sched: bypass heuristic checks when regpressure tracking is disabled.

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mi-sched: Reuse an invalid HazardRecognizer to save compile time.

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mi-sched: Load clustering is a bit to expensive to enable unconditionally.

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mi-sched: Suppress register pressure tracking when the scheduling window is too small.

If the instruction window is < NumRegs/2, pressure tracking is not
likely to be effective. The scheduler has to process a very large
number of tiny blocks. We want this to be fast.

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80 columns

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mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.

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-view-misched-dags, better pruning.

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Remove dead subtree limit code.

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comment typo

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Expand and rewrite comment.

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