Permit changing of verilog dumpvars filename
Mend ISIM failure to find .mif initialisation file

This file may be wiped out by a core regeneration, so be careful. For
some reason ISIM in 14.4 does not find ipcore_dir/GenedBlockMem.mif
unless the ipcore_dir part of the path is explicitly specified.
Wait longer to start up clocks (for ISIM)
Delay startup until clocks come alive, properly
Four stage multicycle execution on posedge

All parts of design operating on posedge, with four cycles per
instruction. ISE indicates nearly 44MHz top speed now that the
negedge-posedge path is removed and additional signals are registered,
but the multiplier is producing incorrect results again as before.
Explicit single-cycle memory cycle at cyc[2]
Step up clock to 40MHz

With the new 4-cycle instructions, this is an even 10MIPS. Runs on
hardware and in simulation solidly.
Merge branch 'multicyc' into develop