Fix a tblgen subtargetemitter bug, for future Swift support.

This fixes some of the ridiculously complex code for optimizing the
machine model tables that are shared among all processors of a given
target. A9 and Swift both use the "special" feature that maps old
itinerary classes to new machine model defs. They map different
overlapping subsets of instructions, which wasn't handled correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183302 91177308-0d34-0410-b5e6-96231b3b80d8
The GNU/HURD is also using the libc. Therefor, endian.h should be included, not machine/endian.h. See full build log https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=hurd-i386&ver=1%3A3.3~%2Brc3-1~exp1&stamp=1370358869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183303 91177308-0d34-0410-b5e6-96231b3b80d8
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
SubtargetEmitter fix

Don't output data if we are supposed to ignore the record.

Reapply of 183255, I don't think this was causing the tablegen segfault on linux
testers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183311 91177308-0d34-0410-b5e6-96231b3b80d8
ARMInstrInfo: Improve isSwiftFastImmShift

An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183314 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Add divsion, loads, branches, vfp cvt

Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Add more ALU and CMP instructions

Reapply of 183258.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
Represent symbols with a SymbolIndex,SectionIndex pair.

With this patch we use the SectionIndex directly, instead of counting the
number of symbol tables. This saves a DenseMap lookup every time we want to
find which symbol a relocation refers to.

Also simplify based on the fact that there is at most one SHT_SYMTAB and one
SHT_DYNSYM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183326 91177308-0d34-0410-b5e6-96231b3b80d8
[PATCH] Fix VGATHER* operand constraints

Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183328 91177308-0d34-0410-b5e6-96231b3b80d8
yaml2obj: add -format=<fmt> to choose input YAML interpretation

See the comment in yaml2obj.cpp for why this is currently needed.
Eventually we can get rid of this, but for now it is needed in order to
make forward progress with adding ELF support, and should be
straightforward to remove later.

Also, preserve the default of COFF, to avoid breaking existing tests.
This policy can easily be changed later though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183332 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] brcond + setgt/setugt instruction selection patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
yaml2obj: split out COFF logic into separate file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183335 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Schedule copy from phys register at beginning of block

It allows regalloc pass to remove them by trivially assigning associated reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
Don't hide the first ELF symbol.

The first symbol on ELF is dummy, but it has a defined content and readelf
normally displays it. With this change llvm-readobj also displays it and we
can check that llvm-mc output is correct according to the standard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183337 91177308-0d34-0410-b5e6-96231b3b80d8
[ELF] Add ELFOSABI_GNU.

ELFOSABI_LINUX is a historical alias for ELFOSABI_GNU according to
<http://www.sco.com/developers/gabi/latest/ch4.eheader.html>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183339 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Add link to SysV ABI document.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183341 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Add link to C++ ABI document.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183342 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add a pass that merge Vector Register

Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
Add writeAsBinary(raw_ostream &) method to BinaryRef.

Previously, yaml2coff.cpp had a writeHexData static helper function to
do this, but it is generally useful functionality.

Also, validate hex strings up-front to avoid running having to handle
errors "deep inside" the yaml2obj code (it also gives better diagnostics
than it used to).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183345 91177308-0d34-0410-b5e6-96231b3b80d8