Added pocl and TCE blurbs to the ReleaseNotes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181001 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Add target description for btver2; make autodetection logic aware of AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add llvm::Triple::systemz

First step towards reinstating the SystemZ backend.  Tests will be
included in the main backend patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181007 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add ELF relocation support

Another step towards reinstating the SystemZ backend.  Tests will be
included in the main backend patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181008 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for reading ARM ELF build attributes.

Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.

Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009 91177308-0d34-0410-b5e6-96231b3b80d8

[SystemZ] Support System Z as host architecture

The llvm::sys::AddSignalHandler function (as well as related routines) in
lib/Support/Unix/Signals.inc currently registers a signal handler routine
via "sigaction".  When this handler is called due to a SIGSEGV, SIGILL or
similar signal, it will show a stack backtrace, deactivate the handler,
and then simply return to the operating system.  The intent is that the
OS will now retry execution at the same location as before, which ought
to again trigger the same error condition and cause the same signal to be
delivered again.  Since the hander is now deactivated, the OS will take
its default action (usually, terminate the program and possibly create
a core dump).

However, this method doesn't work reliably on System Z:  With certain
signals (namely SIGILL, SIGFPE, and SIGTRAP), the program counter stored
by the kernel on the signal stack frame (which is the location where
execution will resume) is not the instruction that triggered the fault,
but then instruction *after it*.  When the LLVM signal handler simply
returns to the kernel, execution will then resume at *that* address,
which will not trigger the problem again, but simply go on and execute
potentially unrelated code leading to random errors afterwards.

To fix this, the patch simply goes and re-raises the signal in question
directly from the handler instead of returning from it.  This is done
only on System Z and only for those signals that have this particular
problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181010 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add MCJIT support

Another step towards reinstating the SystemZ backend.  I'll commit
the configure changes separately (TARGET_HAS_JIT etc.), then commit
a patch to enable the MCJIT tests on SystemZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181015 91177308-0d34-0410-b5e6-96231b3b80d8
Remove comment that no target supports 128-bit IEEE floats

The soon-to-be-committed SystemZ port uses 128-bit IEEE floats.
MIPS64 GNU/Linux does too (albeit with unusual NaNs).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181016 91177308-0d34-0410-b5e6-96231b3b80d8
CMake: cxxabi.h is only available to C++ compilers, use the right check macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181019 91177308-0d34-0410-b5e6-96231b3b80d8
RegionInfo: Do not crash if unreachable block is found

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181025 91177308-0d34-0410-b5e6-96231b3b80d8
Autoconf: Compile cxxabi.h in C++ mode.

Should fix PR15877.

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R600: Clean up comments in Processors.td

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R600: Add pattern for SHA-256 Ma function

This can be optimized using the BFI_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
R600: BFI_INT is a vector-only instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Expand vector or, shl, srl, and xor nodes

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LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming values.
By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements.

We can now vectorize this loop:

int foo(int *A, int *B, int n) {
  for (int i=0; i < n; i++) {
    int x = 9;
    if (A[i] > B[i]) {
      if (A[i] > 19) {
        x = 3;
      } else if (B[i] < 4 ) {
        x = 4;
      } else {
        x = 5;
      }
    }
    A[i] = x;
  }
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181037 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Split the DSP control register and define one register for each field of
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
Decompose GVN::processNonLocalLoad() (about 400 LOC) into smaller helper functions. No function change. 

This function consists of following steps:
   1. Collect dependent memory accesses.
   2. Analyze availability.
   3. Perform fully redundancy elimination, or 
   4. Perform PRE, depending on the availability

 Step 2, 3 and 4 are now moved to three helper routines.


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[PowerPC] Add assembler parser

This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux.  The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated.  (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings.  The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector. 
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features.  When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Support extended mnemonics in AsmParser

This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser.  It adds support specifically for those
extended mnemonics that LLVM will itself generate.

The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.



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