hdl/*: (1/2) Add registers to filter outputs and fix monit. rate

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)
models/*: (2/2) Add registers to filter outputs and fix monit. rate

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)