tcg-ppc: fix qemu_ld/qemu_st for AIX ABI

For the AIX ABI, the function pointer and small area pointer need
to be loaded in the trampoline.  The trampoline instead is called
with a normal BL instruction.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
tcg-ppc: use new return-argument ld/st helpers

These use a 32-bit load-of-immediate to save a mflr+addi+mtlr sequence.
Tested with a Windows 98 guest (pretty much the most recent thing I
could run on my PPC machine) and kvm-unit-tests's sieve.flat.  The
speed up for sieve.flat is as high as 10% for qemu-system-i386, 25%
(no kidding) for qemu-system-x86_64 on my PowerBook G4.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
configure: Allow command-line configure for ppc32

Similar to manually selecting i386 for an x86_64 host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Cleanup tcg_out_qemu_ld/st_slow_path

Coding style fixes.  Use TCGReg enumeration values instead of raw
numbers.  Don't needlessly pull the whole TCGLabelQemuLdst struct
into local variables.  Less conditional compilation.

No functional changes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Use conditional branch and link to slow path

Saves one insn per slow path.  Note that we can no longer use
a tail call into the store helper.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Fix and cleanup tcg_out_tlb_check

The fix is that sparc has so many mmu modes that the last one overflowed
the 16-bit signed offset we assumed would fit.  Handle this, and check
the new assumption at compile time.

Load the tlb addend earlier for the fast path.

Remove the explicit address + addend and make use of index addressing.

Adjust constraints for qemu_ld64 such that we don't clobber the address
register or tlb addend before loading both values.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Use ldrd/strd for appropriate qemu_ld/st64

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Rearrange slow-path qemu_ld/st

Use the new helper_ret_*_mmu routines.  Use a conditional call
to arrange for a tail-call from the store path, and to load the
return address for the helper for the load path.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Use strd for tcg_out_arg_reg64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Use QEMU_BUILD_BUG_ON to verify constraints on tlb

One of the two constraints we already checked via #if, but
the tlb offset distance was only checked at runtime.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Move load of tlb addend into tcg_out_tlb_read

This allows us to make more intelligent decisions about the relative
offsets of the tlb comparator and the addend, avoiding any need of
writeback addressing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Return register containing tlb addend

Preparatory to rescheduling the tlb load, and changing said register.
Continues to use R1 for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Remove restriction on qemu_ld output register

The main intent of the patch is to allow the tlb addend register
to be changed, without tying that change to the constraint.  But
the most common side-effect seems to be to enable usage of ldrd
with the r0,r1 pair.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Move the tlb addend load earlier

There are free scheduling slots between the sequence of
comparison instructions.  This requires changing the
register in use to avoid conflict with those compares.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Reformat tcg-target.c

Whitespace and brace changes only.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: More use of TAI and SAI helper macros

Finish conversion of all memory operations.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCG_REG_Rn constants

Instead of bare N, for clarity.  The only (intentional) exception made
is for insns that encode R|0, i.e. when R0 encoded into the insn is
interpreted as zero not the contents of the register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use tcg_out64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>