target-arm: A64: add support for ld/st pair

This patch support the basic load and store pair instructions and
includes the generic helper functions:

  * do_gpr_st()
  * do_fp_st()
  * do_gpr_ld()
  * do_fp_ld()
  * read_cpu_reg_sp()
  * gen_check_sp_alignment()

The last function gen_check_sp_alignment() is a NULL op currently but
put in place to make it easy to add SP alignment checking later.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

Changes
  - merge ldp/stp together
  - add read_cpu_reg_sp() and use
  - only reference registers as needed
  - use common tcg ops for gpr/fp loads/store
target-arm: A64: add support for ld/st unsigned imm

This adds support for the forms of ld/st with a 12 bit
unsigned immediate offset.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

Changes
   - split off cpu_read_reg_sp for earlier use
target-arm: A64: add support for ld/st with reg offset

This adds support for the load/store forms using a register offset.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: add support for ld/st with index

This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (which are all
variations on the same 9-bit immediate instruction form).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: add support for add, addi, sub, subi

Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>

---
Changes:
  - remove pointless mov op (we already have a copy)
target-arm: A64: add support for move wide instructions

This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: add support for 3 src data proc insns

This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
Changes:
  - Use tcg ops for mul[su]h (rh comment)
target-arm: A64: implement SVC, BRK

Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add decoder skeleton for FP instructions

Add a top level decoder skeleton for FP instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: implement FMOV

Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Update generic cpreg code for AArch64

Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder

The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the
environment pointer around everywhere the way the 32 bit decoder
does. Adjust the parameters these functions take so that we can
copy only the relevant info from the CPUARMState into the
DisasContext and then use that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement MRS/MSR/SYS/SYSL

The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"
such as cache maintenance which in AArch32 are mixed
in with other cp15 registers. Implement these instructions
to look in the cpregs hashtable for the register or
operation.

Since we don't yet populate the cpregs hashtable with
any registers with the "AA64" bit set, everything will
still UNDEF at this point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement minimal set of EL0-visible sysregs

Implement an initial minimal set of EL0-visible system registers:
 * NZCV
 * FPCR
 * FPSR
 * CTR_EL0
 * DCZID_EL0
 * TPIDR_EL0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
default-configs: Add config for aarch64-linux-user

Add a config for aarch64-linux-user, thereby enabling it as
a valid target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v1 -> v2:
   - Make it take vaargs for fmt as not all decoders follow the dame form
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60

---

v3 -> v4 (ajb):
   - use new ld_gpr api

v4 -> v5 (ajb):
   - fixup commenting style
target-arm: A64: WIP support for ld/st exclusive

XXX: not up-streamable as is - still has failure modes

This implement exclusive loads/stores for aarch64 like for arm32 and
ppc.  loads remember the address and loaded value, and stores throw
an exception which uses those values to check for equality in a proper
exclusive region.

AArch64 also implements new aquire/release loads/stores without the
exclusive part, which merely imposes an ordering on memory operations.
As we run on just one CPU, that's not necessary, but could be done
e.g. by a simple heavy barrier insn.

from Alexander Graf <agraf@suse.de> aarch64 series 12/60
 and Michael Matz <matz@suse.de> aarch64-1.6 branch
 and Peter Maydell <peter.maydell@linaro.org> aarch64 clean-up

---

v3 -> v4 (ajb):
   - use new gpr_ld API

v4 -> v5 (ajb):
   - merge in later fixes from Matz
   - fix bug with using ZR for status
   - add sp alignment check
   - fixup bogus whitespace
target-arm: A64: add support for conditional compare insns

this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: add support for add/sub with carry

this patch adds support for C3.5.3
Add/subtract (with carry)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>