msm: clock: backport updates from CAF msm-3.4 - part 2
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msm: clock-8960/8660/9615: Fix pcm clock initial rate

If the pcm clock is not handed off via clock handoff the rate of
pcm is set to 0. In this case, clk_set_rate() of zero would not
program the hardware to select the external input. Therefore set
the rate of the clock to some large initial value so that
clk_set_rate(0) will work properly.

Change-Id: I2555cf2bd1984e8ede5a2b537a3a7dd60034fcf5
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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msm: clock-8xxx: Duplicate gfx2d frequency table for gfx2d1

The gfx2d clocks are getting stuck off randomly when the clock
is turned on. With clocks that are glitch-free dual banked clocks
we use the frequency tables to store information about the mn
enable bits. At compile time, both mn enable bits are set in the
frequency pointer (BIT(8) | BIT(5)). At runtime, the mnd_en_mask
is updated to reflect the current bank that's selected. The
mnd_en_mask is used to turn on the mn counter for the bank that's
being used.

This is all fine except that for gfx2d there are two clocks and
these two clocks share the same frequency table. This means that
gfx2d0 can change its rate and land on bank0 and gfx2d1 can
change its rate and land on bank1. If the two clocks are "out of
phase" and one clock is using bank0 and the other clock is using
bank1 we'll get into a situation where the frequency table will
reflect settings for one clock configured for bank0 and when we
go to enable the clock on bank1 it will program the incorrect
mn enable bit.

When this occurs the clock will have its correct bank chosen but
the mn counter will be off and the counter mode will not be
bypass. This will cause the bank to never turn on and then the
clock will get stuck.

Duplicate the tables so that both gfx2d cores can be used at the
same time and not conflict.

Change-Id: Idb5fc584211e941284b02dc3d964fe2bab2bf377
CRs-Fixed: 333496
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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msm: clock: Fix rate storage for pll/pll_vote/fixed clocks

pll_clk, pll_vote_clk and fixed_clk have a separate rate field in
their definition structs. This is redundant since the clk struct
embedded in these three clocks has the rate already. In addition,
there is a problem of finding the correct vdd level while update
the vdd for the pll clk which support vdd voting because the level
is found by looking at the rate in the clk struct instead of the
rate outside of clk struct.

Therefore, remove the rate field for these clocks and update the
corresponding get_rate functions.

Change-Id: Iff21488cb7f45447949674ce0bf7543482463bfe
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
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msm: clock-local: Remove rcg_clk_get_rate()

This function is no longer necessary because clk_get_rate() looks
in the clk structure to return the last set rate if there is no
get_rate op. Remove it to save some code space.

Change-Id: I4d7a76bc03fc6c11d4b26b77b53ebbcd3588d9a3
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>