started scheduling DMA transfers (and it seems to work from the DMA side)
but I have no idea yet what is happening on the actual SPI bus - no logic analyser available to me right now.
Still there is something strange because the RX DMA seems stuck for some reason...

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
next version - that still shows issues - even with the "workarround"...
CS goes High, while it should stay low...

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
got an initial version (almost) working
still missing is the "schedule" multiple transfers (and the possible optimizations therof)

also got a delay_usec implemented that hopefully does not waste too many CPU/bus resources - it is based on DMA, but still other DMAs with higher priorities may interrupt this DMA...
it seems to be exact to about 1% - did not yet measure jitter or long-term stability...
Still it should be better than the linux delay - especially if one includes the overhead for scheduling the worker hread that then would enable the DMA...

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>