Fix swapped definitions of (UFix / Fix) and (UFix % Fix)
Don't fold signed operators

The folding code is only correct for unsigned operations.
For C++, specify mul/div destination width

This allows the destination width to be set independently of the input widths.
Implement signed-by-unsigned mul/div in terms of signed-signed mul/div

Verilog doesn't natively support these operations directly, so we were generating incorrect code.