xilinx_spips: Fix QSPI FIFO size

QSPI has a bigger FIFO than the regular SPI controller. Differentiate
between the two with correct FIFO sizes for each.

This is the first piece of class data for SPIPS, so this patch sees
the creation of the XilinxSPIPSClass definition and assoicated QOM
constructs.

---CHANGELOG---
changed from v3:
removed space after sizeof (PMM review)
changed from v1:
Reimplemented using class data (PMM review)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Trash LQ page cache on mode change

Invalidate the LQSPI cached page when transitioning into LQSPI mode.
Otherwise there is a possibility that the controller will return stale
data to the guest when transitioning back to LQ_MODE after a page
program.

---CHANGELOG---
changed from v2:
Removed extraneous break after goto (PMM review)
changed from v1:
Re-implemented using separate SPI/QSPI write handlers.
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Add automatic start support

SPI has a mode where it automatically starts based on tx fifo
occupancy. Implemented.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Implement automatic CS

Implement the automatic CS control feature. If the MANUAL_CS bit is
cleared then the chip select stay de-asserted as long as the tx FIFO
is empty.

---CHANGELOG---
changed from v3:
remove usage on DB_PRINT_L (PMM review)
changed from v1:
Refresh CS on entry and exit from flush routine as needed.
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: lqspi: Dont touch config register

The LQSPI mode is supposed to work via the automatic CS mode feature
rather than manipulate CS lines itself. Now that auto CS is implemented
remove LQSPIs CS mode override logic. There is still a need to
manipulate the U_PAGE bit in LQSPI config register to implement
dual-stack mode however.

---CHANGELOG---
This patch in new as of v2
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Fix CTRL register RW bits

The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.

---CHANGELOG---
changed from v1
Macroified magic number (PMM review)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Fix striping behaviour

The QSPI controller was using byte-wide stripes when striping across
the two flashes in dual parallel mode. The real hardware however uses
individual bit striping. QEMU misbehaves in the (corner) case where
data is written/read in dual-parallel mode and read/written back in
single mode.

---CHANGELOG---
changed from v1:
comment the stipe function (PMM review)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Debug msgs for Snoop state

This is worth keeping track of when debugging the device model.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: Multiple debug verbosity levels

The debug printfs on every SPI operation is extremely verbose. Add
a second level of debug for this.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: lqspi: Push more data to tx-fifo

Do 16 words per fifo flush. Increases performance and decreases
debug verbosity. This data depth has no real hardware analogue,
so just go with something that has reasonable performance.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
xilinx_spips: lqspi: Fix byte/misaligned access

The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word wise accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
HACK: ssi: autoconnect: Specify start and how many

Specify the index of the first child to autoconnect and how many.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: xilinx_spips: Changed hardcoded chip selects

Changed the number of chip selects avaliable per bus to 1. This disables the
stacking functionality of the controller, limiting the controller to single
flash and dual-parallel flash modes.

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
COVER: Xilinx SPIPS fixes round 2

---CHANGELOG---
Updates to the Zynq SPI controller. Some QOMifying cleanup, followed by
a number of bugs/incompletnesses found by some (very) rigourous test
vectors.

changed from v4:
Address PMM review (P5 and P8)
changed from v3:
Fixed break after goto (PMM review)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>