ValueTracking: Fix bugs in isKnownToBeAPowerOfTwo

(add nsw x, (and x, y)) isn't a power of two if x is zero, it's zero
(add nsw x, (xor x, y)) isn't a power of two if y has bits set that aren't set in x


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185954 91177308-0d34-0410-b5e6-96231b3b80d8
Don't crash in SE dealing with ashr x, -1

ScalarEvolution::getSignedRange uses ComputeNumSignBits from ValueTracking on
ashr instructions. ComputeNumSignBits can return zero, but this case was not
handled correctly by the code in getSignedRange which was calling:
  APInt::getSignedMinValue(BitWidth).ashr(NS - 1)
with NS = 0, resulting in an assertion failure in APInt::ashr.

Now, we just return the conservative result (as with NS == 1).

Another bug found by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185955 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:

1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.

2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.

3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.

The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
Attempt to appease buildbot after r185956 by explicitly turning setting -fma,-fma4 attrs (I'm assuming they're set because the bot is running on machine that has one or the other.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185958 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Better fix for PR16556.

A more complete example of the bug in PR16556 was recently provided,
showing that the previous fix was not sufficient.  The previous fix is
reverted herein.

The real problem is that ReplaceNodeResults() uses LowerFP_TO_INT as
custom lowering for FP_TO_SINT during type legalization, without
checking whether the input type is handled by that routine.
LowerFP_TO_INT requires the input to be f32 or f64, so we fail when
the input is ppcf128.

I'm leaving the test case from the initial fix (r185821) in place, and
adding the new test as another crash-only check.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185959 91177308-0d34-0410-b5e6-96231b3b80d8
WidenVecRes_BUILD_VECTOR must use the first operand's type

Because integer BUILD_VECTOR operands may have a larger type than the result's
vector element type, and all operands must have the same type, when widening a
BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type, but
rather must use the type of the existing operands.

Another bug found by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185960 91177308-0d34-0410-b5e6-96231b3b80d8
Appease Atom buildbot after r185956 (explicitly turn on AVX)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185961 91177308-0d34-0410-b5e6-96231b3b80d8
Appease buildbots after r185956: just set -mcpu explicitly, as it should have been from the beginning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185962 91177308-0d34-0410-b5e6-96231b3b80d8
Added "mode: c++" to FastISel.h header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185963 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed up the comments in FastISel.h so that they conform to the LLVM style guide.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185964 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply an improved version of r180816/180817.

Change the informal convention of DBG_VALUE machine instructions so that
we can express a register-indirect address with an offset of 0.
The old convention was that a DBG_VALUE is a register-indirect value if
the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE
is register-indirect if the first operand is a register and the second
operand is an immediate. For plain register values the combination reg,
reg is used. MachineInstrBuilder::BuildMI knows how to build the new
DBG_VALUES.

rdar://problem/13658587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185966 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PR16571, which is a bug in the code that checks that all of the types in the bundle are uniform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185970 91177308-0d34-0410-b5e6-96231b3b80d8
Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185971 91177308-0d34-0410-b5e6-96231b3b80d8
move test into the appropriate subdir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185972 91177308-0d34-0410-b5e6-96231b3b80d8