hdl: fix TX clock domains

The prodocution board has a dedicated TX clock that is a twin of the TX clock
pin used by LMS. The FPGA should clock TX samples against a clock that uses
c4_tx_clock as a reference.
fx3_firmware: add GET INTERFACE handling

For some reason the Cypress library does not properly keep track of the current
interface.
fx3_firmware: fix UART DMA channel destruction

A typo causes one of the DMA channels to escape being destroyed.
CyU3PUartDeInit() should called when the UART is torn down.
Merge remote-tracking branch 'gh-nuand/bladerf' into dev-cli
lib: Allow reloading of FPGA