When the store FIFO in the L2 cache bus interface begins to get full (writeback_queue_almost_full), it suspends accepting new requests from cores on the L2 interface.  However, this signal was also used to qualify enqueue_i, which would mean that writeback requests would get dropped (presumably I was thinking that this signal would stall the L2 pipeline when I originally implemented it, then later realized that would deadlock and instead made the signal route to the arbiter stage).

This is hard to test for in the simulation test harness, because most of them auto flush the L2 cache.  However, it was very evident in the 'whack' FPGA test, which does a lot of stores. The L2 cache bus interface is an area that in general does not get a lot of test coverage in simulation and has had a number of bugs.

random3.hex cosimulation test fails.  However, it failed also before this change, so it must have been broken by some previous change.  Need to fix that.