COVER: R5: PMSAv7 First pass implementation

First Pass at PMSAv7 MPU as implemented by cortex-r5. Created a mock
processor "cortex-r5" that implements the PMSA.

Wojciech, whats the state of BURST + R5? Can we carve off the MPU tests
and throw them into a very minimal R5 BURST and run this?

Future work:
Init the R5 processor properly
Ronaldo RPU Machine Model (with OCM and TCMs)

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup

The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm/helper.c: Implement MIDR aliases

Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm/helper.c: Allow const opaques in arm CP

Allow for defining const opaque data in ARM CP register definitions by
setting .opaque = foo. If non null opaque is passes into
define_one_arm_cp_reg_with_opaque then that opaque will take
precedence, otherwise if null opaque is passed, the original opaque
data will be used.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>