Martin's new adat_out, not yet integrated.
Switch DSP core to negedge reset also. Unfortunately it still treats 'start' as an asynchronous reset too.
Make the sample memory a circular buffer. Saves four instructions per biquad, which is one third of total.
Document the misnamed 'accumulator load' instructions.
We call it logic, not reg, these days.
This code will run on DSP v2. Now to write DSP v2...
Merge branch 'master' into experimental
Initial (non-working) commit of new mixer HDL
Renamed coeff to param to match assembler
Changed instruction memory interface to simple instruction input port (assumes PC is external to dsp_core)
Removed most references to offset
changed instruction internals (including adding opcodes in current assembler)
Split up control logic.
Remove param mif stuff
remove instruction decode and just pipeline instruction word itself
Remove program counter (now external to dsp_core)
Change to new fixed-point format, and make it general.
Added opcode decoding; also fixed some little things (leftover PCs), did a little renaming, and removed the instruction input in top.sv so it synthesizes
added more reset logic
added inter-core bus output in writeback stage