wb_fmc516/*: add ADC clock synch'ed reset
various: rename wishbone and common folders

Now, custom_wishbone is dbe_wishbone and custom_common is dbe_common
various: change wishbone and common references
hdl/ip_cores/general-cores: update submodule reference
hdl/modules/fmc-adc-common/*: first commit of fmc-adc-common

This is inteded to be a general FMC ADC framework
for building firmware for FMC ADC boards, such as
the fmc130m_4ch, fmc250m_4ch and fmc516
hdl/modules/*/wb_fmc516/*: convert fmc516 codes to fmc-adc-common
hdl/top/*/dbe-fmc516/*: small fixes to adapt top module

This is necessary once we have changed some wb_fmc516
interfaces, due to the use of the fmc-adc-common
hdl/syn/dbe_bpm_fmc516/*: update synthesis files
hdl/modules/*/wb_rs232/*: add rs232 wishbone master
hdl/*/wb_fmc130m_4ch/*: add fmc130m_4ch module
hdl/top/*/dbe_bpm_fmc130m_4ch/*: add top files for fmc130m_4ch
hdl/syn/dbe_bpm_fmc130m_4ch/*: add syn files for fmc130m_4ch
hdl/modules/*/wb_stream_generic_pkg.vhd: change default WBS input vector
emb-sw/*/fmc516.c: change channel 3 delay to 28
hdl/modules/*/fmc_adc_clk.vhd: fix BUFIO/BUFR generation for 7 series FPGA
hdl/top/*/dbe_bpm_dsp.vhd: use wishbone wrapper for position_calc core
hdl/ip_cores/dsp-cores: update submodule reference
hdl/Manifest.py: comment out rffe_top module
hdl/ip_cores/general-cores: update submodule reference
Merge branch 'fmc-adc-devel' into dsp-devel

Conflicts:
	embedded-sw/fmc/fmc516/fmc516.c
	hdl/Manifest.py
	hdl/modules/custom_wishbone/Manifest.py
	hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
	hdl/syn/dbe_bpm_fmc516/make_output