First steps for tic6x 16 bits opcode disassembly

The tic6x architecture supports 16 bits opcode format for a subset of its
instructions. This is a try to add support for those while trying to stick
to the existing tic6x code base.

This work is based on various Texas Instruments documents and mainly the
TMS320C674x DSP CPU and Instruction Set Reference Guide (sprufe8b.pdf)

- add an INSN16FLD macro to hold 16 bits instruction format definition
that all have a s bit at bit 0.
- add definition for l3xc and sbs7c instruction formats to the format table.
- add bnop (sbs7c) and cmpeq (l3xc) to the opcode table.
- convert the 'flags' field from short to int to increase the flag space
- elect to encode the opcode modifiers requirements (found in fetch packet
header: BR, SAT, DSZ) as flags.
- add TIC6X_COMPACT_PRED flag to denote the use of compact instruction
predicate register (restricted to A0 A1 B0 and B1).
- add a code paragraph to handle the TIC6X_COMPACT_PRED and decode the
correct predicate register.
- add some hack-ish displays to instrument the code as debugging help.
16 bits instruction disassembly - continued
16 bits instruction disassembly - 11/20/2012
16 bits instruction disassembly - 11/23/2012
16 bits instruction disassembly - 11/26/2012
16 bits instruction disassembly - 11/26/2012
16 bits instruction disassembly - 11/28/2012
16 bits instruction disassembly - 11/29/2012
16 bits instruction disassembly - 11/29/2012
16 bits instruction disassembly - 11/30/2012
16 bits instruction disassembly - 12/01/2012
16 bits instruction disassembly - 12/03/2012
16 bits instruction disassembly - 12/03/2012
16 bits instruction disassembly - 12/04/2012
16 bits instruction disassembly - 12/05/2012
16 bits instruction disassembly - 12/06/2012
16 bits instruction disassembly - 12/08/2012
16 bits instruction disassembly - 12/09/2012
16 bits instruction disassembly - 12/11/2012
16 bits instruction disassembly - 12/12/2012