Fixed bug in one-bit voting
Attempt at fixing liaison with one cycle delay.

Introducing the one cycle delay affected the input_active
signal, which lasted one cycle too long. The signal was
used to decide between data and status for output, so we
could not just set it to 0 one cycle earlier. This could be
fixed by adding another register to delay the value of
input_active for muxing purposes, but we are beginning to get
a lot of registers, and the design is getting a lot more complex.

I am also not sure whether the design will work with di_ready
pulses of 11 cycles or not, but I do not think it does at the
moment. This is because the di_ready pulse will cause the liaison
to select data instead of the final status bit which it has not yet
sent... BUT not if we delay the input_ready signal with the register
as discussed in the previous paragraph! Will try to do that now...

If that does not work, then perhaps reverting to the non-delayed
solution would be better, implementing a latch to control the
one bit voter enabling.
Added input_active delay, fixes first four test cases and proper enabling of one bit voter
Completed test case of consecutive data input