msm_fb: display: fix underrun seen due to scaling accuracy

When making scale phase step ratio calculation, accuracy is lost when
sizes are big since calculation is done in 32 bit and some truncation
happens; this leads to underrun in mdp hw since scaling ratio doesn't
match the src/dst rectangle. Increase accuracy by performing division
again on remainder and appending to lsb of ratio.

Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
(cherry picked from commit 1af8a35b8700d507016d6c05488401dbf6af0431)

Change-Id: Ifb2166833db74ae3c37640e5efb9c7a2e0d88209
Signed-off-by: Zhoulu Luo <zluo@codeaurora.org>
v4l: add fourcc definitions for compressed formats

Add fourcc definitions and documentation for the following
compressed formats: H264, H264 without start codes,
MPEG1/2/4 ES, XVID, VC1 Annex G and Annex L compliant.

Change-Id: Ibd87db4f72793310871ebd7a178e9593c4b54d33
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Deva Ramasubramanian <dramasub@codeaurora.org>
(cherry picked from commit 8b02007a6b8887182b3b783518e0620922070e94)
v4l: Add frameskip parameter

v4l2_qcom_frameskip is a QCOM specific parameter to be used with
VIDIO_S_PARM to indicate that the driver might take up to
maxframeinterval nanoseconds in providing the next buffer.

Driver supports this parameter if the V4L2_CAP_QCOM_FRAMESKIP capability
is set in VIDIO_G_PARM.

Change-Id: Iebbd012b9cc75395b1e165349e7e2d9d7a77160a
Signed-off-by: Deva Ramasubramanian <dramasub@codeaurora.org>
(cherry picked from commit 51cbd0accc560b8941ab7c25f4a838f233bf301a)
mfd: pm8xxx-misc: Fix pm8xxx_smpl_control so that reset on SMPL works

pm8xxx_smpl_control currently sets power-off register values in
both the power-off and reset code paths for PM8018 and PM8921.
Correct this so that reset on sudden momentary power loss
(SMPL) works properly.

CRs-Fixed: 336620
Signed-off-by: David Collins <collinsd@codeaurora.org>
(cherry picked from commit c06e0d6283ece540e7a21618f3585e71a5d4dda0)

Change-Id: I7eae8a781a9651778ada48f82f939dd40a7e196f
Signed-off-by: Ramakrishna Prasad N <crpn@codeaurora.org>
msm: allow memory pools to be created from multiple memory banks

On platforms which require very large memory pools, it
might not be possible to create such a memory pool from
a single memory bank (even though there may be several
contiguous memory banks of the same memory type), and
the memory pool created would then be smaller than requested.

Allow multiple contiguous memory banks to be used in the
creation of memory pools, making it more likely that a
large memory pool can be created of the desired size.

CRs-Fixed: 333361
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
(cherry picked from commit 48e4f5f31c19f1b9e5f54cdba61beeec434c8c56)

Change-Id: I51a033e65bd42bd65f85b09c0d1700f142be2108
Signed-off-by: Yen-Pin Hsiao <yphsiao@codeaurora.org>
msm: clock-8xxx: Duplicate gfx2d frequency table for gfx2d1

The gfx2d clocks are getting stuck off randomly when the clock
is turned on. With clocks that are glitch-free dual banked clocks
we use the frequency tables to store information about the mn
enable bits. At compile time, both mn enable bits are set in the
frequency pointer (BIT(8) | BIT(5)). At runtime, the mnd_en_mask
is updated to reflect the current bank that's selected. The
mnd_en_mask is used to turn on the mn counter for the bank that's
being used.

This is all fine except that for gfx2d there are two clocks and
these two clocks share the same frequency table. This means that
gfx2d0 can change its rate and land on bank0 and gfx2d1 can
change its rate and land on bank1. If the two clocks are "out of
phase" and one clock is using bank0 and the other clock is using
bank1 we'll get into a situation where the frequency table will
reflect settings for one clock configured for bank0 and when we
go to enable the clock on bank1 it will program the incorrect
mn enable bit.

When this occurs the clock will have its correct bank chosen but
the mn counter will be off and the counter mode will not be
bypass. This will cause the bank to never turn on and then the
clock will get stuck.

Duplicate the tables so that both gfx2d cores can be used at the
same time and not conflict.

CRs-Fixed: 333496
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit ff8f57f46a0485a0a19809af7847a16136564298)

Conflicts:

	arch/arm/mach-msm/clock-8960.c

Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>
(cherry picked from commit e0fe23da200cea58a6363b8bd2791136399b64d7)

Change-Id: I2a4d97164a4e1128ac640a5880a8108f9c3aed28
Signed-off-by: Yen-Pin Hsiao <yphsiao@codeaurora.org>