add ring3 dbg to project and customization of r0 one
pusha popa reg passing logic updated; communication with r3 component introduced
tracing of r3 app introduced
branch tracing : LBR bugfix -> TOS stack usage + correct src-dst ip established
refactoring! + bugfixes; TODO : AVL double free bug in destructor
tracing via python
LBR per CPU (HV); proc->thread callback event logic
Branch trace + python == full coverage; Thread boundaries resolved correctly for r3 threads; x86 to x64 (&vice versa) calls problem resolved; call to special modules logic