Starting implementing AST errors for semantic checker
Pretty printer formatting fix
Fixed major bug in dynamic array creation, caught by guzheng
Added full test coverage for uintms
Improve error messages for union
initial work on z80
Minor bugfix/format change in z80
Added state machine macro
Add "and" and "or" to piplin

This makes an eager "and" and "or" operation that are synthesizable.
This commit also makes "deserialize" synthesizable.
When iverilog compile fails, throw exception

Before, we were actually throwing a File Not Found exception when vvp
tried to run the code, which obfuscated the issue--syntax error.
Add verilog for "not", improve conversion error msgs
Example VGA generator

Taken from MIT's 6.111 course notes
Added sints type without verilog conversion
Add binary representation of sints
Add verilog synthesis of sints addition

Also changed verilog compiler to allow statements to include additional
temporaries or other lines.
Add full support for multiplication and sign extension of sints
Whitespace cleanup
Add kinds for java float and double
Add signed saturating fixed points

This includes addition, subtraction, and multiplication. Addition and
multiplication are synthesizable and tested.
Prune zero-length bitfields in bit-cat verilog gen