OMAP: ID: introduce chip detection for OMAP4460

Add support for detecting the latest in the OMAP4 family: OMAP4460
Among other changes, the new chip also can support 1.5GHz A9s,
1080p stereoscopic 3D and 12 MP stereo (dual camera). In addition,
we have changes to OPPs supported, clock tree etc, hence having a
chip detection is required.

Starting from OMAP4460 ES1.0, we are moving from HAWKEYE to Ramp system
for chip identification. Since the bit offsets are the same, just rename
the variable for dual use.

For more details on OMAP4460, see
Highlights:
http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=53243&navigationId=12843&templateId=6123
Public TRM is available here as usual:
http://focus.ti.com/general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123&navigationId=12667

[nm@ti.com: cleanups and introduction of ramp system]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
OMAP4: PRM: OMAP4460 specific PRM and CM register bitshifts

This patch adds additional register bitshifts for
registers added in OMAP4460 platform.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4: hwmod: make current hwmods common for 4460 and 4430

Make all hwmod data used for OMAP4430 available for
the OMAP44XX class so that OMAP4460 can use them.
We will modify the required 4460 hwmod in further patch(es).

[nm@ti.com: just rebased to .39]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
OMAP4460: hwmod: Do not reset GPIO1 during hwmod init

For OMAP4460, GPIO-7 of bank1 is used for controling
the TPS modes, hence GPIO1 should not be reset
during init as reset will cause the TPS voltage to
drop to 0.9 V.

IMPORTANT: this patch has been rejected upstream:
http://marc.info/?t=130637509100002&r=1&w=2
Recommendation is: omap_hwmod_no_setup_reset in board files
we fork in that respect to make it easier for boards following
TI reference schematics.

Originally from:
http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=52ae4f0de03b17c064d9ce90a580230f1a596ec1

[nm@ti.com: upstream version]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Moiz Sonasath <m-sonasath@ti.com>
OMAP4: hwmod: differentiate 4430 and 4460 bandgap

OMAP4430 and 4460 have slightly different functional clocks.
we need to map this back into hwmod database as well to ensure
sanity.

Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: clocks: distinguish 4430 and 4460

OMAP4460 platform has a few clock nodes which are added
and a few which are missing (compared to the 4430 platform)
rename current 4430 definitions to 44XX and followon patches
will introduce the 4460 changes

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4: clocks: Update the clock tree with 4460 clock nodes

OMAP4460 platform has a few clock nodes which are added
and a few which are missing (compared to the 4430 platform)
Update the clock tree accordingly and handle these nodes
using the clock flags (CK_*).

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4: powerdomain: Update MPU powerdomain for 4460

The 4460 platform has changes in the MPU powerdomain,
hence model a new powerdomain for it and identify
is using the CHIP_IS_OMAP446X macro.
Also move all the common powerdomains to use
CHIP_IS_44XX so they are reused on OMAP4460.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4: clockdomain: Reuse on 4460 using CHIP_IS_44XX

The 4460 platform has no difference in the clockdomains as compared
to the 4430 platform. Hence just update the .omap_chip field to make
sure the same clockdomains model data can be reused on the 4460 platform.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4460: dpll: Support MPU frequencies > 1 Ghz

The OMAP4460 platform needs DCC (Duty cycle correction)
enabled for frequencies above 1GHz from the MPU DPLL.

Also on 4460, the MPU clk for frequencies higher than 1Ghz
is sourced from CLKOUTX2_M3, instead of CLKOUT_M2, while
value of M3 is fixed to 1. Hence for frequencies higher
than 1 Ghz, the dpll should be locked at half the rate
so the CLKOUTX2_M3 out then matches the requested rate.

To do this a virtual clock node 'virt_dpll_mpu_ck' is
modeled, which has custom recalc, round_rate and set_rate
functions implemented which handle all the above
requirements.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
OMAP4460: dpll: Control async bridge to ABE and L3/MA to EMIF

On OMAP4460 when the MPU Frequency is above 748Mhz,
the programmable divider for the Async bridge to ABE must be
set to MPU-Freq/8. For lower frequency, it should be MPU-Freq/4.

Similarly for MPU Frequency above 920Mhz, the programmable divider
for the async bridge to L3 and Memory Adapter interfaces of EMIF
must be MPU-Freq/4. For lower frequency, they should be MPU-Freq/2.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4: PM: Handle 4460 clk name delta for mpu

The DPLL for MPU should now be dpll_mpu_ck instead of
virt_dpll_mpu_ck for 4460.

Reported-by: Colin Cross <ccross@google.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4: OPP: add OMAP4460 definitions

Add OMAP4460 OPP definitions for voltage and frequencies based on
OMAP4460 ES1.0 DM Operating Condition Addendum Version 0.1

The following exceptions are present:
* Smartreflex support is still on experimental mode: the gains and min
  limits are currently pending characterization data. The values are picked
  up currently from TI's Kernel 2.6.35:
  git://git.omapzoom.org/kernel/omap.git p-android-omap-2.6.35-4460-wip dcfa2a4
* Efuse offset for core OPP100-OV setting is not clear in documentation and
  seems to be not supported in K35
* IVA OPPs beyond OPP100 are disabled due to the delta between max OMAP4460
  current requirements and Phoenix Max supply on VCORE2 in the default
  configuration - boards which have supply which can support this should
  explicitly call opp_enable and enable the same.
* MPU OPPs > OPPTURBO can easily be detected using a efuse burnt - currently
  disabled pending clock cleanups.

[nm@ti.com: cleanups and updates from Datamanual and k35 source]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Merge branch 'v3.0-4460-fixes' into omap-pm-integration
OMAP4: L2X0: Update PL310 register bits for OMAP4460

On OMAP4460, L2 double line fill feature is available.
Enable the same along with optimal POR offset.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4460: L2X0: Temporary work-around for stability.

OMAP4460 ES1.0 seems to suffer from stability with L2 cache enabled.
The root-cause analysis is ongoing but in meantime this chabe is
to enable a software WA with L2 cache enabled build. The WA consist
of locking certain cache ways based on their positions on the
physical memory layout.

Downside of this WA is that effective L2 cache size will be 512 KB
instead of 1 MB.

Of course this is temporary WA and needs to removed once the root
cause and the right fix is found.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4: PM44: Handle 4460 clk name delta for mpu

The DPLL for MPU should now be virt_dpll_mpu_ck instead of dpll_mpu_ck
for OMAP4460. Fix this for idle changes

Reported-by: Colin Cross <ccross@google.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP4460: cpufreq: Use the virtual clock node to scale MPU

4460 has a new virtual clock node modeled to handle DCC and
other async bridge dependencies.
Make cpufreq use the virtual node for scaling.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4460: OPP: Update MPU and IVA dependency

Define new tables for 4460 specific MPU and IVA voltage
dependencies.

Also uncomment the 4430 specific dependencies since CORE voltage
scale is functional now.

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
OMAP4460 cleanup static def nonstatic prototype

Signed-off-by: Andy Green <andy.green@linaro.org>