lspci: Decode PCIe Link registers only for devices with links

Root Complex Integrated Endpoints and Root Complex Event Collectors do not
have links and are not permitted to implement Link or Link 2 registers,
per PCIe spec r3.0, sec 1.3.2.3.  Decoding them is useless and misleading.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"

The PCIe Link Capabilities "L0s Exit Latency" is the latency to exit
L0s, not L0, so label it "L0s" instead of "L0".  This matches the
way we label the Device Capabilities "Endpoint L0s Acceptable Latency"
field as "Latency L0s".  This also adds "Exit" to the description to
help distinguish it from the "Acceptable Latency" fields in the
Device Capabilities register.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Decode PCIe DevCap "Acceptable Latencies" only for Endpoints

The PCIe Device Capabilities "Endpoint L0s Acceptable Latency" and
"Endpoint L1 Acceptable Latency" are defined only for Endpoint functions,
so don't display them unless this is an endpoint.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Decode PCIe DevCap/DevCtl FLReset only for Endpoints

The PCIe Device Capabilities and Control bits related to Function
Level Reset are valid only for Endpoints, so only decode them in
that case.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Clarify "PCIe-to-PCI/PCI-X" desc and Bridge Retry Config Enable

The PCI_EXP_TYPE_PCI_BRIDGE type is a PCIe to PCI/PCI-X bridge, so be a bit
more complete in the comment and printed device type.  Also, per PCIe spec
r3.0, Table 7-14, the PCIe Device Control "Bridge Configuration Retry
Enable" bit only applies to PCIe-to-PCI/PCI-X bridges; it does not apply to
PCI-to-PCIe bridges.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Decode PCIe LnkCtl "Read Completion Boundary" for PCIe-to-PCI bridges

The PCIe spec (r3.0, Table 7-16) says the Read Completion Boundary is valid
for Root Ports, Endpoints, and Bridges.  I only added decoding for PCIe-to-
PCI/PCI-X bridges because the RCB of a Bridge indicates the RCB of the
upstream Root Port, so I don't think it makes sense for PCI-to-PCIe
bridges.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
lspci: Drop PCIe LnkCtl "Retrain Link" decoding

Per PCIe spec r3.0, Table 7-16, the Retrain Link bit is writable but
always returns 0 when read, so decoding it gives no useful information.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
sysfs: Do not warn on incomplete slot addresses

Based on a patch by Zheng Huai Cheng <zhenghch@linux.vnet.ibm.com>.
Updated pci.ids to today's snapshot
Released as 3.2.1.