AVX-512: Moved {er} decorator position next to the last SIMD op

This is for following the current syntax used in gas even though
this is not SDM conforming.
According to SDM, {er} should follow the last GPR op not SIMD op.
e.g. SDM : VCVTSI2SD xmm1, xmm2, r/m64{er}
    NASM : VCVTSI2SD xmm1, xmm2{er}, r/m64

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Find the correct position of the last SIMD op

Since embedded rounding mode is following the last SIMD op,
GPR op should be skipped when finding the last SIMD op.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Fix a bug in calculating Disp8*N value

Fixed a bug that derived an incorrect N value for tuple types of
T2, T4, T8.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Change the data type for instruction flags

Increased the size of data type for instruction flags from 32bits to 64bits.
And a new type (iflags_t) is defined for better maintainability.

Bigger data type is needed because more instruction set types are coming
but there were not enough space for them. Since they are not bit masks,
only one instruction set is allowed for each instruction.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Fix match function to check the range of registers

High-16 registers of XMM and YMM need to be encoded with EVEX not VEX.
Even if all the operand types match with VEX instruction format,
it should use EVEX instead.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add a test case for EVEX encoded instructions

This was converted from a gas testsuite.
(gas/testsuite/gas/i386/x86-64-avx512f-intel.d)
A python script that is used for converting is also included.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add a feature to generate a raw bytecode file

From gas testsuite file, a text file containing raw bytecodes
is useful when verifying the output of NASM.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Remember the position of operand with broadcast or embedded rounding

It was not so straight forward to find the postion of operand that has
a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions)
decorator out from operands types or bytecode.
Remebering the postion of the operand of interest in the parser reduces
the burden that assembler looks through the operands.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Fix comments

Fixed or purged some old comments and added a comment for a previous patch.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Fix bug in checking high-16 registers

Register value needs to be checked. Previous patch compared with reg_enum.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add IF_SPMASK and fix IF_PFMASK

Defined IF_SPMASK for specific processor types and
fixed IF_PFMASK to mask the exact preferred bits only.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add OPMASK instructions

Added opmask instructions (kandw and etc). Defined KREG and RM_K
aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat
look neat.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Remove trailing space and align columns

Cosmetic change

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add test case for opmask instructions

Added K* instructions test cases in test/avx512f.asm.
The previous test case from GNU AS were repeating the same instruction twice,
so the repeated half part is removed.
Changed the python script (gas2nasm.py) to include opmask instructions.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Fix rounding mode value in EVEX prefix with SAE

If SAE is set, VL(vector length) is implied to be 512.
EVEX.L'L (=EVEX.RC) is set to 00b by default.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Reorder instructions in insns.dat

Within a same instruction mnemonic, instructions are reordered
in order of opcode byte value.
Therefore when there are two possible opcode candidates, smaller
opcode is picked now.
e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add Pseudo-ops for CMP instructions

Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on.
Test case is also updated to validate them.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add AVX-512CD instructions

Added Conflict Detection (AVX-512CD) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Add AVX-512ER instructions

Added Exponential and Reciprocal (AVX-512ER) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1.
IF_AVX512 is now shared by all AVX-512* instructions as a bit mask.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
AVX-512: Added AVX-512PF instructions

Added Prefetch (AVX-512PF) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1.
CPUID feature flag for PREFETCHWT1 is TBD
but PREFETCHWT1 is included in this commit.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>