STM32 F3 I2C driver from John Wharington
Add ARMv7-A irqdisable() inline function
More DAC changes from John Wharington
The last bit of a previous commit was still in the editor
ARMv7-A:  Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM
SAMA5: Change mapping of vector tables to work around that fact that I don't understand how the AXI MATRIX remap works
Fix Cortex-A CPSR register field definition
SAMA5: Modification of some CPSR-related inline functions
SAMA5: Add an NSH configuration of the SAMA5D3x-EK board
SAMA5:  Delay loop calibrated; Correct sense of the RED LED
Prep for NuttX-6.29 release
Correct errors noted in SAMA5 documentation
ARMv7-A:  Separate CONFIG_PAGING start-up logic into a different startup file.  Too much conditional compilation.
ARMv7-A:  Map all of .text, .bss, .data., stacks before enabling the MMU and caching. This is simpler and avoids fears I have about caching
SAMA5:  Add DDR controller register definitions
SAMA5:  Add logic to initialize SAMA5D3x-EK on-board SDRAM
SAMA5:  More MMU-related changes to properly initialize SDRAM
Correct some typos int he MPADDRCS register address definitions
Various changes to get SAMA5 SDRAM working.  Marginally functional, but there is more to be done
Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts