Implemented biquad filter in verilog.  With constants as inputs, it takes up 13% of tht FPGA.  Needs memory interface for coefficients and to be tested with real coefficients for a filter with a real input.
Both memory windows have been tested and work fine, both bram modules have been tested and work fine as well.  Needs biquad communication module that will talk to both brams, load coefficients into the filter, and log the appropriate values
32bit biquad filter has been implemented, along with bram storage for logging accumulator values and coefficient storage.  Memorywindows have been implemented for both brams, which are accessible from the linux command line.  ADC buffers have been added, however are not used yet.  DAC module needs to be implemented along with a decimator and filter for the sigma delta stream.
Contains single biquad implementation.  Coefficient blockram is functional, logging is not implemented yet.
Added a few comments to clear up some module functions.  DAC output filter is implemented, but has not been characterized or tested.  Probably doesn't work at all.  Project file was updated and cleaned up a bit.
Fixed syntax error in biquad module.  No other changes.

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=== FIRST COMMIT FOR BOARD V2 ===

- New spi_module.v to replace old dac_spi_module.  Includes control for shift register on board.  Shift register portion is tested and works.
- DAC portion untested
- pga_control.v skeleton file added
- All DIO's mapped properly in top file to appropriate wires
- Some older files that were not added/committed are now committed.
Changes:
- PLL's modified, main now provides 50MHz clock for SPI module,
  removed second port on secondary PLL.  Need to investigate
  which PLL's are actually needed for full functionality.
- Peripheral_control.v skeleton file added.  Going to be used as
  a parent module to the spi module and pga module.  Will handle
  startup conditions, calibration, and DAC output.
Changes:
- PGA module now generates 5MHz SPI clock
- PGA state machine skeleton set up
- PGA module instantiated in top module
Committing latest code from end of June '12.  VLIW machine and virtualized filer implemented but not working completely.
Added all the files created from last commit
Added most recent version of the project, includes docs folder with datasheets, XP2 verilog primitives from the XP2 IP cores, and the newest files (including simulation files) for the FPGA code
Fixed Modelsim file to use relative paths defined in MGC_LOCATION_MAP file under the label $flexSD.  Please update/create the file accordingly.

Removed extra project files associated with previous hard paths.
Fixed Sigma Delta Test Modelsim Project to use relative paths.  Uses the same $flexSD variable from MGC_LOCATION_MAP.
Sigma Delta folder was showing that it wasn't added for some reason
Merging latest branch into master so it is the working copy

Conflicts:
	ts7500/opencore/syscon.v
	ts7500/opencore/ts7500_top.v

Took copies of above conflicts from the 'latest' branch, since those are the changes we want