changed to ANSI style ports, replaced regs with logics
.* port connections
remove 'num_to_bitvector' function which was only used one time
cleaned first 2 always blocks
 - now use always_comb (this is what AUTOSENSE was supposed to accomplish)
 - got rid of ridiculous case statements used for bit shifting, replaced with shifts
 - used ternary where reasonable
 - replaced complicated if/else with case, result on line 248
begin work on first sequential block
 - finished reset section
 - grouped signals with like reset levels, allowing '1 and '0 assignemnts
reworking always_ff block
 - attempted to comment basics of code
 - removed unnessesary begin/ends
 - used concatenation and ternaries where appropriate
 - replaced bizarre if/else tree with a 2-bit case
   - which will infer latches, but the original code did that too
the great whitespace massacre
 - fix ALL the indenting!!
finished second sequential block. minor fixes throughout
went over third sequential block... not much to do there
not much to change in RegAddr block
small tweaks to ReqWEL/RegWEH block, removed some warnings
cleaned up the bus block case statements
cleaned up control signal block
very little to change in second control signal block
simplified sync input block
finished rest of blocks in tv_80 core
Merge branch 'cpu' of github.com:rattboi/gateboy into cpu