ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp -- If CONFIG_SMP, cpufreq skips loops_per_jiffy update, because different arch has different per-cpu loops_per_jiffy definition.
cpufreq: interactive: Sync with Google's 3.4 kernel
USB: android: Prevent change of host mac address of 'rndis0' interface
Perf: Restore correct CPU's PMU counters after power collpase

Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.

Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add event name to output

If PMU's are accessed by names, this patch will make 'perf stat'
also output the name of the event along with the PMU name.

Change-Id: If62b5eaf8340c94c797644389cfd5d937b7a5a25
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Make L1 PMU IRQ name target independent

Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.

Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add generic IRQ handlers for ARMv7 PMU's

For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.

Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
coresight: only use etm0 for populating configuration

With maxcpus=1, only core0 will be running with other cores in
reset until they are explicitly hotplugged on. To avoid reading
ETM registers for cores that are in reset during probe, use only
ETM0 for populating configuration info. For other ETM probes,
copy the info from ETM0.

Change-Id: I9ae4539b004956a026e919323413f9e3c7d5ba4a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: allow usage of all ports for 8064

8064 funnel has 8 ports so allow all to be used. Typo corrections.

Change-Id: I2a442048a2100ab07f34d453f538f89babd9d514
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight: change to using smp call for etm enable/disable

Since we moved to separate enable nodes for each ETM, using pm_qos
to prevent power collapse of the target cpu while we enable or
disable ETM is less efficient and also susceptible to a race with
cpu hotplug.

Move to using smp call to enable and disable trace to avoid above
deficiencies with the newly re-structured code.

Change-Id: I65c726dbd6275af8db0d40db5034299287a02e91
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's
gpu: ion: Return error value when iommu map fails

When __ion_map_iommu returns a non-zero value (i.e.
error occured), properly propagate this error back
up to the client.

Change-Id: I6cd5ce8a723ad1cbbd6c42b712f5a19fa2ba719f
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
gpu: ion: Add response to secure scm call

The API for securing buffers now requires a response buffer.
Pass in the appropriate buffer and size.

Change-Id: I25ed77f539e775b089c71a96120edf37132acd0d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>