ARM: dts: msm: Disable HSIC controller clock gating for MDM9625

Clock gating is by default enabled in HSIC controller.
This is resulting in stability issues during enumeration.
Hence, disable clock gating in the HSIC controller.

Change-Id: Id7b68d83da43a6050be509a489c6aa601bf87f72
CRs-fixed: 538509
Signed-off-by: Amit Blay <ablay@codeaurora.org>
USB: dwc3: Fix QDSS data integrity issue

Currently RAM12, RAM13 are being used for data fifo and
descriptor fifo allocations in QDSS BAM <-> BAM usecase. Remaining
16KB out of 29KB is being used for allocation of TX FIFO for
USB IN endpoints in the composition. This resulting in data corruption
when captured with host side application. Due to this, QTF host
application is not able to parse the data collected over USB.
Hence reserve RAM11, RAM12, RAM13 for 16KB data fifo allocation and
5KB descritor fifo allocation in QDSS mode and use remaining 8KB for
TX FIFO allocation for IN endpoints.

As available tx fifo size is reduced in QDSS mode, allocate 1KB for
bulk and isochronous endpoints in highspeed mode and also for nonburst
endpoints in superspeed mode. For burst endpoint in superspeed mode,
allocate 3KB for TX FIFO.

CRs-Fixed: 553147
Change-Id: I6d50d2da631a95a921c47bb1fb1139477840a73c
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
msm: pm: Prevent system sleeps when suspend is in progress

The MPM driver sends a XO vote for suspend during suspend prepare
callback. If the CPU were to execute a system low power mode after
suspend, the MPM driver votes against XO shutdown based on the list of
enabled interrupts. This vote is never removed and results in the XO
vote for shutdown overridden by the idle parameters.

Fix issue by ensuring that the system doesn't enter system low power
mode when the device is preparing for suspend. This would also prevent
RPM power collapse as RPM could turn off XO based on state of the
suspend votes sent as a part of suspend_prepare.

CRs-fixed: 551806
Change-Id: I9104f28898c995f69b8c0b9124651b915e15f690
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
usb: dwc3-msm: Support LPAE for DBM

On LPAE-enabled systems, BAM data FIFO addresses may be
36-bits wide, hence use phys_addr_t to store them. Such
addresses then need to be written to two separate 32-bit
QSCRATCH registers.

Change-Id: I00be6024c050ff0f6c105094c08c60387bc1109c
Signed-off-by: Jack Pham <jackp@codeaurora.org>
usb: usb_bam: use correct props structure

usb_bam_init() prepares the sps_bam_props structure prior
to registering it with the SPS driver. However it is
inadvertently making a local copy due to the assignment

   struct sps_bam_props props = ctx.usb_bam_sps.usb_props;

such that when the function exits, these values are lost.
This is not causing a functional problem, as the copy in
ctx.usb_bam_sps is not used outside of this function, but
for debugging purposes it would be useful to inspect the
values later. Fix this by simply using a pointer to assign
to ctx.usb_bam_sps.usb_props directly.

Also fix a debug printk that appears in a switch case statement,
as it does not apply to the fallen-through case above.

Change-Id: Idf6a3d33a206a0ab55e5cb3bfa25a2ef38b038a9
Signed-off-by: Jack Pham <jackp@codeaurora.org>
ARM: dts: msm: Enable USB BAM on APQ8084

Enable USB BAM device for the SS USB core, which allows for
BAM-enabled USB transfers for functions such as QDSS. Also
fix the following:

- the FIFO base address should be specified as a 32-bit value
- the data FIFO offset to the USB3 controller's internal memory
  was pointing to the wrong address
- add TX FIFO size parameters specifying the available memory in
  the USB3 controller both when QDSS is enabled and disabled

Change-Id: I35eee4c4c2d747aad9b9f25b4005cc3e3cb1c477
Signed-off-by: Jack Pham <jackp@codeaurora.org>
ARM: dts: msm: add rtb to device tree for samarium

Add support to device tree node to enable RTB logging on samarium.
RTB logging provides useful debug information by logging events to
uncached buffer which can be processed from ramdumps in case of device
reset.

Change-Id: I77795826a80d63103b41e65aacaf3f1e6eeb8e6d
Signed-off-by: Aparna Das <adas@codeaurora.org>
ARM: dts: msm: update documentation for rpm-smd property.

Meaning of rpm-standalone property got changed after
I102b06420fdfa1505d8f43e8936a8e9cee4f1ce4. Updated the
documentation as per latest usage.

Change-Id: I067527b31db102d09be39324c9e656ed741798c5
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
ARM: dts: msm: tune LPM parameters for 8226v1 and v2

Platform PM driver takes LPM parameters as one of the input
and decide the best idle system low power mode. Current LPM
parameters are not optimal and this can lead to more power
consumption for APPS proc active usecases. This change tunes
the low power mode parameters such as "latency",
"time overhead", "steady state power" and "energy overhead"
for 8226v1 and 8226v2.

CRs-fixed: 506262
Change-Id: Iecfc1d7f722c8416b70ddf4c447a5050f0c1187c
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: spm: add intermediate LPM mode for L2 PC

Currently when the core decide to enter into "PC + L2 PC"
LPM mode it informs to RPM and there is a chance of
system can enter into either XO or VDDmin. But this LPM
mode take longer time to enter and exit. Because of this
limitation some of the usecases where there is a less
latency APPS proc stays at lower LPM level (i.e GDFS) and
causing more power consumption. To address this issue adding
an intermediate LPM mode where L2 goes to PC but not inform
to RPM.

CRs-fixed: 552743
Change-Id: I321ff260d5baf8ac44917d67e9c9dfd260c8d5ca
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
ARM: dts: msm: add intermediate LPM level for 8226v1 & v2

Current LPM mode levels are not sufficient to reduce the
power consumption on all the APPS proc usecases(e.g HSDPA).
To address this adding a new LPM level wich takes less time
to collapse the APPS proc and L2 cache. Also this mode will
not inform the RPM about APPS PC state.

CRs-fixed: 552743
Change-Id: I9511c147b85c21693636a2667c9040f111a9e9bf
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
ARM: dts: msm: Add qseecom device for msmsamarium

Add device tree entries for the qseecom driver.

Change-Id: Id8e1f5e469b89a9e2fb7b9219be6acd049110259
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
msm: clock-krypton: Fix error handling in measurement code

Release the spinlock if there is an invalid measument entry.
Remove the invalid entries from the table.

Change-Id: I9870bb77d812a9452a2bac2eb06e76bdffc70706
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: clock-krypton: Add clocks for usb

Add the PMIC xo buffer and sleep clocks.

Change-Id: Iecfe5b7d2fa9b8c1c13437870c708c882de96c23
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: acpuclock-8226: Update Speedbin mappings

The HW Speedbin mappings have changed. Update SW accordingly.

Change-Id: I1ebb668eba53d4adf8063260f9cf7b8dc6ba4a19
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Merge "ARM: dts: msm: tune LPM parameters for 8226v1 and v2"
Merge "msm: spm: add intermediate LPM mode for L2 PC"
Merge "ARM: dts: msm: add intermediate LPM level for 8226v1 & v2"
Merge "ARM: dts: msm: Add qseecom device for msmsamarium"
Merge "ARM: dts: msm: Disable HSIC controller clock gating for MDM9625"