Clarify comments in genLoopLimit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193292 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed llvm-cov to count edges instead of blocks.

This was a fundamental flaw in llvm-cov where it treated the values in
the GCDA files as block counts instead of edge counts. This created
incorrect line counts when branching was present. Instead, the edge
counts should be summed to obtain the correct block count.

The fix was tested using custom test files as well as single source
files from the test-suite directory. The behaviour can be verified by
reading the GCOV documentation that describes the GCDA spec ("ARC_COUNTS
gives the counter values for those arcs that are instrumented") and the
header description provided by GCOVProfiling.cpp ("instruments the code
that runs to records (sic) the edges between blocks that run and emit a
complementary "gcda" file on exit").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193299 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in LinearFunctionTestReplace that created invalid loop exit checks.

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193303 91177308-0d34-0410-b5e6-96231b3b80d8
Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cases. Some of these may have been tested by other tests, but most weren't. Patch by Cameron McInally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193309 91177308-0d34-0410-b5e6-96231b3b80d8
Add non-AVX tests for AES intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193310 91177308-0d34-0410-b5e6-96231b3b80d8
Replace sse41/sse42 with sse4.1/sse4.2 in test command lines to fix bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193311 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193312 91177308-0d34-0410-b5e6-96231b3b80d8
Include missing Compiler.h for using LLVM_ENUM_INT_TYPE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193315 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.

When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
fix PR17635: false positive with packed structures
LLVM optimizers may widen accesses to packed structures that overflow the structure itself, but should be in bounds up to the alignment of the object

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193317 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure SP is always aligned on a 2 byte boundary


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193320 91177308-0d34-0410-b5e6-96231b3b80d8
Added test for -elf configuration, to see that _alloca call is properly 
generated. See:

http://llvm.org/viewvc/llvm-project?view=revision&revision=193289



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193321 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix assert on unpredictable POP instruction.

POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.

With some vigorous hand-waving in the error message both problems can be
fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
Revert part of r193291, restoring the deletion of loaded objects.
Without this, customers of the MCJIT were leaking memory like crazy.

It's not really clear what the *right* memory management is here, so I'm
not trying to add lots of tests or other logic, just trying to get us
back to a better baseline. I'll follow up on the original commit to
figure out the right path forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193323 91177308-0d34-0410-b5e6-96231b3b80d8
Replaced non-ASCII character.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193324 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Use non-VFP softcalls on embedded Darwinish targets

The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1
code to make use of VFP instructions by switching back to ARM mode, they make
no sense for M-class processors which don't even have an ARM mode.

Given that justification, in practice this is a platform ABI decision so the
actual check is based on that rather than CPU features.

rdar://problem/15302004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
Added tests for microMIPS relocations 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193332 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: mark various aliases with their architecture requirements.

If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: add a couple more NEON predicates.

The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
Added std::string as a built-in type for mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193344 91177308-0d34-0410-b5e6-96231b3b80d8