import mor1kx_monitor from mor1kx-dev-env

This file is useful for other verification set-ups than mor1kx-dev-env,
by adding it to the mor1kx project we can provide them with the file
without the overhead of acquring the whole mor1kx-dev-env.
cappuccino/fetch: wait out non-cache accesses

When an icache invalidate occur, the icache is muxed away from
ibus and the ongoing fetch is fetched from memory instead of cache.
This access have to finish before we can switch back to fetching
from cache.
cappuccino/lsu: initialize dbus_err on reset
cappuccino/lsu: set dbus_adr to zero when in IDLE state

When running in simulations an uninitialized dbus_adr would
cause X'es to propagate out on the bus.
Since bus arbiters might calculate bus errors from the
address, this could cause X'es to come back on dbus_err_i.
DCache: Non-disrupting invalidation

On the edge of an invalidation request the cache started one
invalidation of the respective tag. By permanently acknowledging the
SPR requests, this had to happen immediately which might corrupt other
processing. Furthermore the edge triggering is not correct as two
succeeding invalidations happen without a low cycle of the spr bus
strobe signal.

The new implementation simply always acknowledges SPR requests while
the invalidation can take place, which is during idle and
invalidation. In all other cases the operation is delayed until the
state machine returns to IDLE. When an invalidation lasts longer, the
respective tag is repeatedly cleared, which is no problem.

Finally, the state machine has been reordered without breaking the
functionality, but for a clear code layout (not overwriting sequential
assignments) and readability.
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). It can apparently not be written.

The multicore core identifier is set via a port, which allows easier
use in verilated models or similar.
Merge branch 'master' into multicore
First work on cache coherency