Revert "xen: start PCI hole at 0xe0000000 (same as pc_init1 and qemu-xen-traditional)"

This reverts commit 9f24a8030a70ea4954b5b8c48f606012f086f65f.

The start of the PCI hole is actually set to 0xf0000000 by hvmloader.
In order to retain ABI compatibility with Xen we leave the start of the
PCI hole at 0xf0000000 in QEMU (for Xen) too.

Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Allow use of pc machine type (accel=xen) for Xen HVM domains.

Xen HVM domains normally spawn QEMU with a dedicated xenfv machine type. The
initialization code for this machine type can easily be pulled into the
generic pc initialization code and guarded with a test for whether the xen
accelerator options is specified, which is more consistent with the way
other accelerators are used.

Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Move hardcoded initialization of xen-platform device.

Creation of the xen-platform device is currently hardcoded into machine
type pc's initialization code, guarded by a test for the whether the xen
accelerator is enabled. This patch moves the creation of xen-platform into
the initialization code of the xenfv machine type. This maintains backwards
compatibility for that machine type but allows more flexibility if another
machine type is used with Xen HVM domains.

Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
target-arm: Allow special cpregs to have flags set

Relax the "is this a valid ARMCPRegInfo type value?" check to permit
"special" cpregs to have flags other than ARM_CP_SPECIAL set. At
the moment none of the other flags are relevant for special regs,
but the migration related flag we're about to introduce can apply
here too.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
    
For reading and writing register values from the kernel for KVM,
we need to provide accessor functions which are guaranteed to succeed
and don't impose access checks, mask out unwritable bits, etc.
Define new fields raw_readfn and raw_writefn for this purpose;
these only need to be provided if there is a readfn or writefn
already and it is not suitable.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: mark up cpregs for no-migrate or raw access

Mark up coprocessor register definitions to add raw access
functions or mark the register as non-migratable where necessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert TCG to using (index,value) list for cp migration

Convert the TCG ARM target to using an (index,value) list for migrating
coprocessors. The primary benefit of the (index,value) list is for
passing state between KVM and QEMU, but it works for TCG-to-TCG
migration as well and is a useful self-contained first step.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Initialize cpreg list from KVM when using KVM

When using KVM, use the kernel's initial state to set up the
cpreg list, and sync to and from the kernel when doing
migration.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Reinitialize all KVM VCPU registers on reset

Since the ARM KVM API doesn't include a "reset this VCPU"
ioctl, we have to capture the initial values of every
register it knows about so that we can reset the VCPU
by feeding those values back again.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Use tuple list to sync cp regs with KVM

Use the tuple list of cp registers for syncing KVM state to QEMU,
rather than only syncing a very minimal set by hand.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Make LPAE feature imply V7MP

The v7 ARM ARM specifies that the Large Physical Address
Extension requires implementation of the Multiprocessing
Extensions, so make our LPAE feature imply V7MP rather
than specifying both in the A15 CPU initfn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Message-id: 1371127899-10364-1-git-send-email-peter.maydell@linaro.org
ARM: Allow dumping of device tree

By calling qemu_devtree_dumpdtb near the end of load_dtb.

Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
i.MX: Implement a more complete version of the GPT timer.

* implement compare 1 2 and 3 registers
* simplify Debug printf

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
Message-id: 1369898943-1993-2-git-send-email-jcd@tribudubois.net
Reviewed-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
i.MX: Rework functions/types name and use new style initialization

* use dynamic cast whenever possible
* Change function names to some more meaningful prefix
* Change type names to a more meaningful one
* use new style device initialization

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
Message-id: 1369898943-1993-3-git-send-email-jcd@tribudubois.net
Reviewed-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
arm/boot: Free dtb blob memory after use

The dtb blob returned by load_device_tree() is in memory allocated
with g_malloc(). Free it accordingly once we have copied its
contents into the guest memory. To make this easy, we need also to
clean up the error handling in load_dtb() so that we consistently
handle errors in the same way (by printing a message and then
returning -1, rather than either plowing on or exiting immediately).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Message-id: 1371209256-11408-1-git-send-email-peter.maydell@linaro.org
i.MX31: Fix PRCS bit test

cppcheck detected a condition which was always false.

According to the MCIMX31 Reference Manual, the PRCS bits have to be 01
to select the Frequency Pre-Multiplier (FPM). PRCS uses bits 1 and 2,
so we have to test for 2.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
Message-id: 1370810662-32320-1-git-send-email-sw@weilnetz.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
block/nand: QOM casting sweep

Define and use standard QOM cast macro. Remove usages of DO_UPCAST and
direct -> style casting.

Cc: afaerber@suse.de

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
block/nand: Convert Sysbus::init to Device::realize

The prescribed transition from Sysbus::init function to a
Device::realize.

Cc: afaerber@suse.de

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
nand: Don't inherit from Sysbus

Nand chips are not sysbus devices - they do not have any sense of MMIO,
nor interrupts. Re-parent to TYPE_DEVICE accordingly.

Cc: afaerber@suse.de

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge remote-tracking branch 'sstabellini/xen-20130625' into staging

# By Paul Durrant (2) and Stefano Stabellini (1)
# Via Stefano Stabellini
* sstabellini/xen-20130625:
  Move hardcoded initialization of xen-platform device.
  Allow use of pc machine type (accel=xen) for Xen HVM domains.
  Revert "xen: start PCI hole at 0xe0000000 (same as pc_init1 and qemu-xen-traditional)"

Message-id: alpine.DEB.2.02.1306251323220.4782@kaball.uk.xensource.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>