Use a pattern matcher to identify possible clock gating. Proof of concept at
this stage.

src:
	* V3Gate.cpp (NodeMatcher, AstMatcher): New classes.
	(GateClockEnGraphVisitor): Add m_gateVar and m_matcher as instance
	variables.
	(GateClockEnGraphVisitor::visit(GateVarVertex *, ...)): Fuller message.
	(GateClockEnGraphVisitor::visit(GateLogicVertex *, ...)): Use
	pattern matcher to identify gating logic.
Merge branch 'gated-clock' of github.com:jeremybennett/verilator into gated-clock