arm: irq: Remove check for hardirq mask size

SPARSE_IRQ gives the freedom to use high, discontiguous IRQ
numbers at very low memory costs. But even with SPARSE_IRQ, the
highest interrupt number of the system is limited by NR_IRQS,
since NR_IRQS defines the number of IRQ_BITMAP_BITS.

NR_IRQS is currently limited to 1024 on ARM, as of the following
commit:

commit 5a5fb7dbe88dd57dc2bef0f3be9da991e789612d
Author: Steven Rostedt <srostedt@redhat.com>
Date:   Thu Feb 12 10:53:37 2009 -0500

    preempt-count: force hardirq-count to max of 10

This implies that architectures having more than 1024 interrupts
cannot manage. Let's remove the constraint on nesting level,
since as the commit above mentions, we're probably bound by stack
size at that point, anyways.

Change-Id: Ic4af331874a8fda66e2c94ef80ad73314badd74d
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
msm: pil-dsps: Assert peripheral reset in addition to proc reset

Failure to assert the peripheral reset in addition to the
processor reset causes state to be maintained across reboots.
Assert the peripheral reset to fully reset the dsps.

Change-Id: I737271a9ffa42253894f83dfd856fb3419ef8275
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
arm: irq: Correct set_irq_flags check for invalid irq

The current check compares against nr_irqs, which is assigned as
machine_desc->nr_irqs if defined. Per the usage in
arch_probe_nr_irqs(), nr_irqs is interpreted to mean the
preallocated irqs when used in a SPARSE_IRQ configuration. So
it's entirely possible that a chip driver will set its IRQ flags
for a IRQ number greater than nr_irqs.

NR_IRQS is still the largest IRQ any system can have, so let's
check for that instead.

Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
tick-sched: change the cpu that updates rq_stats

It can happen that the scheduler tick stops on cpu 0 but keeps
running on some other cpu. Make the cpu in-charge of updating
the jiffies also update the rq_stats.

Change-Id: Idb1a8132bd96500c68c516b4a99663965cec28e1
Signed-off-by: Amar Singhal <asinghal@codeaurora.org>