Added IRef to allow writing to register indexes.
Added toWire and comb functions.
Replaced Data.Bits with Mantle.Bits.

This now gives a representation for types which permits Verilog vectors
to be included. This also replaces the representation of values in the
Expr tree with a new Value datatype which uses an Integer representation,
since this is currently the most common way to create literals. A binary
option for this type may be added in future if it becomes useful.

repType gives a VType for a value, can safely be passed undefined.
repExpr takes a value and gives an Expr representing it.
Added alias Memory for Reg (Vec n a) and index function for lookup.
Avoided Circuit context for index by allowing IRef to take Expr.
Renamed IRef type to RegRef, since it is not used elsewhere.
Added undef and regU, and fixed FIFO.
Unified VecIndex and BitSel as "Index" in Expr.

Since Expr is a syntactic construct there is no reason to disinguish
these currently.
Removed some unnecessary imports.
Split mantle.cabal into lines, and removed some unnecessary depends.
Added operator precedence for (=:).
Added type operator (:->) for functions over Outputs.
Added function inputMap to extend an input with some intermediate logic.
Added fanOut to merge multiple inputs into one.

Also fanOutMap which combines this with inputMap.
Modified Channels to use the new type operator.
Added terminal function, to create an Input which goes nowhere.
Fixed a bug in chanZip which would cause early dequeuing.
Added function chanGuard to guard flow on a condition signal.
Made FlipIfc a member of the Interface type class.
Changed Input to contain type Output a -> Circuit ().