Attempt to optimize total liaison, currently at 29 LUTs.

The optimization consists of extracting common logic for
different parity enable signals, and replacing a LUT
used to calculate reset for should_output_parity_bits
with a calculation in parity-LUTs and a set/reset FF for
the should_output_parity_bits signal.

I am not 100% sure it works, especially the timing seems
pretty risky with state_enable(15) clearing the parity
bits... But I think it works, since all the parity bit
registers are "delayed" 1 cycle.. At least it passes all
tests, both without timing and from post-PnR.