Ensure that globalRegMaybe returns accurate information for XMM registers.
Do not assume that XMM registers are used to pass floating point arguments.

On x86-32, the C calling convention specifies that when SSE2 is enabled, vector
arguments are passed in xmm* registers; however, float and double arguments are
still passed on the stack. This patch allows us to make the same choice for
GHC. Even when SSE2 is enabled, we don't want to pass Float and Double arguments
in registers because this would change the ABI and break the ability to link
with code that was compiled without -msse2.

The next patch will enable passing vector arguments in xmm registers on x86-32.
Enable passing vector arguments in xmm registers on x86-32.

Note that this will only work with the LLVM back end pending LLVM patches to
change the GHC calling convention appropriately.
Do not expose LLVM-only primops in GHC.PrimopWrappers.

GHC.PrimopWrappers is only used by GHCi, which cannot evaluate LLVM-only
primops in any case.
SIMD primops are now generated using schemas that are polymorphic in
width and element type.

SIMD primops are now polymorphic in vector size and element type, but
only internally to the compiler. More specifically, utils/genprimopcode
has been extended so that it "knows" about SIMD vectors. This allows us
to, for example, write a single definition for the "add two vectors"
primop in primops.txt.pp and have it instantiated at many vector types.
This generates a primop in GHC.Prim for each vector type at which "add
two vectors" is instantiated, but only one data constructor for the
PrimOp data type, so the code generator is much, much simpler.
Flesh out 128-bit wide SIMD primops.
Add support for -mavx and -mavx2 flags.
Add Cmm support for 256-bit-wide values.
Add support for 256-bit-wide vectors.
Set LLVM option -stack-alignment=32 when compiling AVX instructions.
Fixup stack spills when generating AVX instructions.

LLVM uses aligned AVX moves to spill values onto the stack, which requires
32-bye aligned stacks. Since the stack in only 16-byte aligned, LLVM inserts
extra instructions that munge the stack pointer. This is very very bad for the
GHC calling convention, so we tell LLVM to assume the stack is 32-byte
aligned. This patch rewrites the spill instructions that LLVM generates so they
do not require an aligned stack.
Pass 256-bit-wide vectors in registers.
Add 256-bit-wide SIMD primitives.
Add support for -mavx512* flags.
Add Cmm support for 512-bit-wide values.
Add support for 512-bit-wide vectors.
Pass 512-bit-wide vectors in registers.
Add 512-bit-wide SIMD primitives.
By default, only pass 128-bit SIMD vectors in registers on X86-64.

LLVM's GHC calling convention only allows 128-bit SIMD vectors to be passed in
machine registers on X86-64. This may change in LLVM 3.4; the hidden flag
-fllvm-pass-vectors-in-regs causes all SIMD vector widths to be passed in
registers on both X86-64 and on X86-32.
Enable -msse to be specified by itself.

This sets the SSE "version" to 1.0.