AArch64: refactor vector list creation to be more uniform

Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a
special register-class to deal with the constraints, and C++ code to support
selection. However, that C++ code can be made reasonably uniform to simplify
the selection process. Hence this patch.

No functionality change, so no tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194361 91177308-0d34-0410-b5e6-96231b3b80d8
Add LLVM_HAS_INITIALIZER_LISTS for upcoming C++11 support.  Use it in ArrayRef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194362 91177308-0d34-0410-b5e6-96231b3b80d8
Don't universally enable initialiser lists on GCC.  Thanks for catching this Chandler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194365 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Blacklist TailDuplicate pass

This causes issues with virtual registers.  We will likely need
to fix TailDuplicate in the future, or introduce a new version
that plays nicely with vregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194373 91177308-0d34-0410-b5e6-96231b3b80d8
[msan] Propagate origin for insertvalue, extractvalue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194374 91177308-0d34-0410-b5e6-96231b3b80d8
[autoconf] Prune "runtime" stuff in configure, corresponding to r191835.

  config.status: executing runtime/Makefile commands
  autoconf/install-sh: runtime/Makefile does not exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194376 91177308-0d34-0410-b5e6-96231b3b80d8
Update of the 'Code Review' page. The link is now called 'Create Diff' instead of 'Create Revision'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194378 91177308-0d34-0410-b5e6-96231b3b80d8
[llvm-c] Remove dead typedef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194379 91177308-0d34-0410-b5e6-96231b3b80d8
[OCaml] Make Llvm_target.DataLayout.t automatically managed

This breaks the API by removing Llvm_target.DataLayout.dispose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194380 91177308-0d34-0410-b5e6-96231b3b80d8
[OCaml] Accept context explicitly in Llvm_target functions

Llvm_target.intptr_type used to implicitly use global context. As
none of other functions in OCaml bindings do, it is changed to
accept context explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194381 91177308-0d34-0410-b5e6-96231b3b80d8
[OCaml] Add missing Llvm_target functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194382 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify code. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194383 91177308-0d34-0410-b5e6-96231b3b80d8
Add PPC option for full register names in asm

On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194384 91177308-0d34-0410-b5e6-96231b3b80d8
Add a testcase for pr17852.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194385 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] CHECK-DAG-ize MSA 2r.ll test.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194386 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] CHECK-DAG-ize MSA 2rf.ll test.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194387 91177308-0d34-0410-b5e6-96231b3b80d8
Move debug message in vectorizer

No functional change, just better reporting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194388 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194389 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194390 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194391 91177308-0d34-0410-b5e6-96231b3b80d8