sha1: code cleanup and use modern C syntax

Apply the following changes:
- Remove out-of-date workaround (SPARC64_GCC_WORKAROUND)
- Use C99 prototype and stdint type

Change-Id: I630cf97f6824f72f4165e0fa9e5bfdad8edabe48
sha1: Use bswap* to optimize byte order

bionic libc already makes use of ARMv6+ rev/rev16 instruction for
endian conversion, and this patch rewrites some parts of SHA1
implementations with swap32 and swap64 routines, which is known to
bring performance improvements.

The reference sha1bench on Nexus S:

[before]
Rounds: 100000, size: 6250K, time: 1.183s, speed: 5.16  MB/s

Change-Id: Id04c0fa1467b3006b5a8736cbdd95855ed7c13e4
[after]
Rounds: 100000, size: 6250K, time: 1.025s, speed: 5.957 MB/sB
Add ARMv7 optimized strlen()

Merge the ARM optimized strlen() routine from Linaro.  Although it is
optimized for ARM Cortex-A9, the performance is still reasonably faster
than the original on Cortex-A8 machines.

Reference benchmark on Nexus S (ARM Cortex-A8; 1 GHz):

[before]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.31712           97        0     1000     1024

[after]
             prc thr   usecs/call      samples   errors cnt/samp     size
strlen_1k      1   1      1.05855           96        0     1000     1024

Change-Id: I809928804726620f399510af1cd1c852ed754403
memcmp: prefetch optimizing for ARM Cortex-A8/A9

The original memcmp() was tweaked for ARM9, which is not optimal for ARM
Cortex-A cores.  This patch merges the prefetch optimizations from
ST-Ericsson and removes NEON slowdowns.

Reference experiement results on Nexus S (ARM Cortex-A8; 1 GHz) using
strbench program:
    http://pasky.or.cz//dev/glibc/strbench/

[before]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.510000 0.000000 2.510000
   8   131072         1.570000 0.010000 1.590000
  32    32768         1.310000 0.000000 1.320000

[after]
size, samples, TIMES[s] - user, system, total)
   4   262144         2.280000 0.000000 2.290000
   8   131072         1.210000 0.000000 1.220000
  32    32768         1.040000 0.000000 1.050000

Change-Id: I961847da96d2025f7049773cd2ddaa08579e78d6
fix ARMv7 optimized strlen() usage condition

Change-Id: Ia2ab059b092f80c02d95ca95d3062954c0ad1023
getopt(): fix missing carriage return on bad parameters

This affect all command line tools which show the usage on stdout
after an invalid parameter error (printed on stderr)

Change-Id: I8e2cb3fda241ab989dc42055f15082f8b3ba1397
Signed-off-by: Tanguy Pruvot <tanguy.pruvot@gmail.com>
headers: Unbreak some ARM syscalls

Restore the outside-kernel exclusion for some syscalls that was
removed by change I959b64280e184655ef8c713aa79f9e23cb1f7df4,
since these syscalls are used elsewhere.

Change-Id: I5b5bf3d78edd137e820d25281a375966b6c009ec
Bionic/libm: fast neon pow() for small x,y

Add a fast neon version of pow() suitable for relatively small
positive x and y (between 0 and 4).  Run the standard
implementation in all other cases.  Gives approximately 60%
performance improvement to AnTuTu FPU score.

Change-Id: I9234d37eaa6a815d1e619375f5b049c4ec88f557
armv6: REX routines are currently broken, use alternatives

Change-Id: I7ac05ab6add7802a4cc24fe36f7181e7cdfe07e0
Bionic/libm: Prefer branches and VFP ABI

For internal functions set gcc attribute "aapcs-vfp" for ARM
and use -fno-if-conversion to prefer branches over predicated
instructions (improves performance on architectures with good
branch prediction).

Change-Id: I365e9508bd3babb0bb06fc5de127c1ae17445bcc
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/ashmemalloc.cpp.

Change-Id: I7b35bcdaedf3874d17a0e6ce18931c11db1e133d
Add missing define to build qcom libgralloc.

This is needed by hardware/qcom/display/libgralloc/pmemalloc.cpp

Change-Id: Id0732b82ed6c1852def9688544ec92e04afeff00
Add missing define for libcopybit.

This is needed by hardware/qcom/display/libcopybit/copybit.cpp.

Change-Id: Ic50a75b93b39443b772dd4cab67a55f75ad2b5ad

Conflicts:
	libc/kernel/common/linux/msm_mdp.h
FORTIFY_SOURCE: remove memcpy overlap checks

These checks haven't been as useful as I hoped, and it's
causing a false positive finding.  Remove the overlap
compile time checks.

Change-Id: I5d45dde10ae4663d728230d41fa904adf20acaea
bionic: Add workarounds for current compilers
With current compilers, we're getting "this function cannot be inlined"
errors on vsnprintf and strlcpy because the always_inline attribute is
set.

Before marking this a "fix" instead of a "workaround", we should figure
out why the functions can't be inlined.

Change-Id: Id6c5464defafb3f9044c102d32a57e70d760b05d
Signed-off-by: Bernhard Rosenkraenzer <Bernhard.Rosenkranzer@linaro.org>
Signed-off-by: Stevespear426 <stephen.k.spear@gmail.com>
Fix assembler error using newer toolchains.
Fixes a ".size expression for pow does not evaluate to a constant" assembler error using linaro 4.7.x.

Change-Id: I5ad3643794df330c0e54508ba946f9fc769e62e2
bionic: Fix aliasing violations

This makes bionic compile with compilers enforcing
strict adherence to aliasing rules (e.g. gcc 4.6+
with -Wstrict-aliasing=2 -Werror=strict-aliasing).

Signed-off-by: Bernhard Rosenkraenzer <Bernhard.Rosenkranzer@linaro.org>
Revert "Add ARMv7 optimized strlen()"

This reverts commit 9b58b97c72f3ec577a1c36dd6ee9a7a3dc9aa589.

Conflicts:

	libc/Android.mk

Signed-off-by: Stevespear426 <stephen.k.spear@gmail.com>
Revert "sha1: Use bswap* to optimize byte order"

This reverts commit d1d19556f6706419c43bc36e6f45fe1027d6195d.
libm: Add a proper sincos() implementation

Add a proper sincos() implementation that unifies the common
calculations for sin and cos instead of running them twice.

This should cause a speedup even in code not using that
(fairly uncommon) function because gcc can optimize separate
sin() and cos() calls into sincos() calls.

Signed-off-by: Bernhard Rosenkraenzer <Bernhard.Rosenkranzer@linaro.org>