changed to sync reset in key_expansion + test, FR

Tested synthesized version of key_expansion with tb_key_key_expansion
and it went out of reset ok.

ncverilog +sv +nc64bit ../tb/tb_key_expansion.sv key_expansion_netlist.v
../../NangateOpenCellLibrary.v
ncverilog(64): 08.10-p002: (c) Copyright 1995-2008 Cadence Design
Systems, Inc.
Loading snapshot worklib.testbench:sv .................... Done
ncsim> source /opt/cadence/IUS81/tools/inca/files/ncsimrc
ncsim> run
key_loaded 1
key_addr 0000
Simulation stopped via $stop(1) at time 2220 NS + 0
../tb/tb_key_expansion.sv:29                    $stop;