Trigger line state check on clock not state change
 - This may be the wrong thing to do, but it removes errors due to
   common data structures
Make state machine more readable
Remove excess logging

Conflicts:

	sw/fpga/targets/rs232/io_rs232.v
Reordered layers to match Sunstone recommendation, improve impedance characteristics of internal signal layers.
Updated layer stack info on PCB document to match Sunstone's recommendation.
Merge branch 'master' of github.com:mossmann/daisho