Enable ATSE_CFI_HACK in BERI configs, stable MAC addresses are useful.

MFC after:	3 days
Sponsored by:	DARPA/AFRL
Add a new function (OF_getencprop()) that undoes the transformation applied
by encode-int. Specifically, it takes a set of 32-bit cell values and
changes them to host byte order. Most non-string instances of OF_getprop()
should be using this function, which is a no-op on big-endian platforms.
MFP4:
Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30

        FreeBSD/mips stores page-table entries in a near-identical format
        to MIPS TLB entries -- only it overrides certain "reserved" bits
        in the MIPS-defined EntryLo register to hold software-defined bits
        (swbits) to avoid significantly increasing the page table memory
        footprint.  On n32 and n64, these bits were (a) colliding with
        MIPS64r2 physical memory extensions and (b) being improperly
        cleared.

        Attempt to fix both of these problems by pushing swbits further
        along 64-bit EntryLo registers into the reserved space, and
        improving consistency between C-based and assembly-based clearing
        of swbits -- in particular, to use the same definition.  This
        should stop swbits from leaking into TLB entries -- while ignored
        by most current MIPS hardware, this would cause a problem with
        (much) larger physical memory sizes, and also leads to confusing
        hardware-level tracing as physical addresses contain unexpected
        (and inconsistent) higher bits.

        Discussed with: imp, jmallett

MFC after:	3 days
Sponsored by:	DARPA/AFRL
MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM

MFC after:	3 days
Sponsored by:	DAPRA/AFRL
Remove a bit of debugging output that slipped into r256911.

MFC after:	3 days
Sponsored by:	DARPA/AFRL
MFP4:
Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08

        Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in
        cache.c into an option and when set force I- and D-cache line
        sizes to 0 (the latter part might be better as a tunable).

        Fix some casts in an #if 0'd bit of code which attempts to
        disable L1 cache ops when the cache is coherent.

Sponsored by:	DARPA/AFRL