Multiplexed low-rate FIR (only multipliers, need to work on adders)
Merge branches 'master' and 'mydevel'
Adding latest models

had been lazy about pushing to git
simulink decided to change the internal version number of this model
even though no actual changes were made.
Added shared memory config files and coefficients.
Changed Python version.
Heap count calculation made general for all modes.
Removed src-new directory after merging changes to src.
add gen_rcs block

General version control block for tracking xblocks_devel, gbt_libraries, and others
Also included 2010b of library since new .mdl was saved in 2012a
Added RCS blocks
Compiled ver115(actually identical to ver100) at 150MHz/800MHz. To Test.
Adding l8_ver102.mdl to the repo and correcting a path mismatch in l1
Added black-box related files for mode l8
Remove the redundant *.log file
Update scripts and added bofs
Added mode_sel for mode l8
Adding l1 fpga design versions 101,102,103,104
Updated scripts for l8_lbw8; removed some out-dated functions
Added relatively cleaned up version of l8; Basically the same as ver104 just re-aligned some blocks, etc.
Revert "Added relatively cleaned up version of l8; Basically the same as ver104 just re-aligned some blocks, etc."

That was a mistake

This reverts commit 4512011263a7f34249ac5659ce613280882405b9.