Remove nHOLD for RAM

Will just tie it high in the circuit.
core_logic: Create separate coprocessor-to-device SPI path

Separate the peripheral SPI interface from the one used to communicate
with MCU and shared serial RAM.

This simplifies the MCU/coprocessor IPC state machine.
core_logic: add buffered USB signals

GPX and INT are from the USB host controller to the coprocessor.

Buffer these signals with the core logic since the USB host controller
pins are not 5V-tolerant, and should not be directly connected to the 5V
coprocessor.
Add SPI memory interface module

This allows a SPI device to access ChronoCube.