Use ASSERT_EQ rather than ASSERT_TRUE for better unit test failures.

Also minor using namespace move so it's not hard-up against the function
definition and outside the namespace as is usual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192744 91177308-0d34-0410-b5e6-96231b3b80d8
Support/FileSystem.h: Remove a trailing comma in enum file_magic::Impl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192745 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up, formatting, comments. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192747 91177308-0d34-0410-b5e6-96231b3b80d8
Add an assert that we have a scope that matters for methods
and remove a call to getNonCompileUnitScope as a method
shouldn't be in the compile unit scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192748 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure we're not attempting to construct a subprogram DIE
twice and just look up the value. Fix the one case where
we were trying to create a subprogram DIE and we should already
have had one. Reflow formatting in collectDeadVariables while fixing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192749 91177308-0d34-0410-b5e6-96231b3b80d8
Enable MI Sched for x86.

This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.

Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.

On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.

Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.

The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.

Unit tests are updated so they don't depend on SD scheduling heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
Fix missing C++ mode thing in header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192751 91177308-0d34-0410-b5e6-96231b3b80d8
Fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192752 91177308-0d34-0410-b5e6-96231b3b80d8