sunxi: UGLY UGLY hack to use the arch timers

The current sunxi-uboot does not properly setup the arch timers (making
their virtual part not usable). This UGLY UGLY patch hacks around this, this
is just a quick hack to see how having better timers helps some other things.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Add driver for SD/MMC hosts found within Allwinner A1X SoCs

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Implement GPIO polling and correct clock handling

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: use clk_sunxi_mmc_phase_control from sunxi-clk driver

Instead of a private copy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Add a few missing register writes / value from the android code

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Cleanup error logging

Don't log error on timeout of opcodes for which a timeout is normal when
using an sd / mmc card. Remove double logging of some errors, and move
logging of data direction to dump_err().

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Remove not-needed and not-working sunxi_mmc_wait_access_done()

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Remove dead code / vars

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Don't mix dma_alloc_writecombine with free_coherent

Use the less exotic (and correct on older ARM cpu cores) dma_alloc_coherent,
note this makes no different on ARMv7.

Also pass in our device pointer to the dma functions, instead of NULL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Get regulator first

Getting the regulator may cause our probing to be deferred, so do it first,
otherwise we may end up calling things like clk_get multiple times until
we succeed, leaking references.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Properly set caps

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Turn on IDMA controller after all setup is done

Specifically set the interrupt mask, and the segment list address before
turning it on. Note the code for setting the segment list address is moved
to a different function entirely, as that needs to be done only once.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Add SD/MMC 0 host device for Allwinner A20

HdG:
Changed drive strength for the mmc / sdio pins from 0 to 2, this is necessary
to make high frequency sdcard/sdio modes work reliable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Enabe MMC 0 for CubieBoard2

HdG:
Dropped the unneeded "reg = <0>;" and related parts from the vcc_3v3_reg
section.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Enable MMC 0 on the cubietruck

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Correctly set sdc0 interrupt type, fixing all the hangs

This is a very small patch, but it took me 2 days to debug, still it was
worth it as this patch has big results, mmc cards now work reliable!

The problem is that the interrupt type for the sdc controller was set
to rising edge (all interrupts are setup this way in sun7i-a20.dtsi, which
likely is wrong).

Setting it to rising edge causes missed interrupts:

1) A request with data is send to the controller
2) The controller finishes the CMD phase of the transaction, this causes
   a bit to be set in the interrupt status register, but this bit is masked
   out, so no interrupt
2) The IDMA controller finishes transferring the data from the request,
   setting its tx or rx complete interrupt status bit, this does cause an
   interrupt
3) The ISR reads the interrupt status register
4) While the ISR is running the hardware completes the data phase of the
   transaction and/or the auto-stop and sets the SDXC_DataOver and/or
   SDXC_AutoCMDDone bits) since this is a request with data these bits
   cause an interrupt, note the interrupt line is already high at this point,
   so no edge!
5) The ISR writes back the interrupt status it has just read, clearing the
   IDMA controller tx or rx complete interrupt status bit. Note the interrupt
   line does not go low, as the SDXC_DataOver and/or SDXC_AutoCMDDone bits have
   not been cleared
6) The ISR exits and does not re-trigger since the interrupt type is set to
   rising edge
7) The block layer now hangs waiting for a request which never completes
   (timeouts are handled in hardware and sets another interrupt status bit)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: dts: sunxi: Fix sunxi-ahci not working on sun4i

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Implement support for mmc on sun4i

While dealing with the amount of bits in the data buf size register anyways,
also properly use all 16 bits of the data buf size on sun5i / sun7i,
rather then only using 15 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Drop waiting for CmdDone flag on RespTimeout

I've tested this and we always end up triggering the timeout, IOW CmdDone
never gets set (within 200 ms) on RespTimeout.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>