msm: vidc: enable video core clock to 266Mhz

This change will ensure that video core clock is
set to 266Mhz on supported devices, else fallback
to 228Mhz.

(cherry picked from commit 2cd6f1a77d845c162966b974b0e9dd4db0878020)

Change-Id: Ib314fc75ff11df04d50a023d39576b8c9fb11371
Signed-off-by: Arun Menon <menon@codeaurora.org>
Signed-off-by: Jessica Gonzalez <jgaona@codeaurora.org>
msm: kgsl: Remove lowest power level

The lowest power level does not correspond to significant
power savings as the whole system doesn't drop to SVS
voltage.  Performace is improved without this level for
serialized test cases.

Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
(cherry picked from commit c8404a799a26f0744d3965822160c7b05b8d33d7)

Change-Id: Ie349451ffcd82f159eb4d25ad0b986b38f817ede
Signed-off-by: Sivasri Kumar Vanka <sivasri@codeaurora.org>
Sound Control: Sound control for WCD93xx codec

Fully GPL'ed version.

Signed-off-by: faux123 <reioux@gmail.com>
slimbus: Fix channel concurrent usage during reconfiguration sequence

Reconfiguration sequence can lead to changes in channel segment
distribution and state. Since multiple clients can use 1 channel,
make sure channels cannot be manipulated when reconfiguration
sequence is in progress, and make sure that client doesn't send
reconfiguration sequence when no changes are pending to be sent
in the sequence from it.

CRs-Fixed: 383406
Change-Id: Ib5f0bc32f67f51f118fa417a2e580c8dc87ef0d0
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
(cherry picked from commit 6e728bd81fbe277b2637f527898d31c2719429db)
slimbus: Decrement channel reference during reconfigure now

Slimbus clients can specify multiple add/remove channel requests
through control_ch API, followed by reconfiguration request (also
known as "commit request"). Clients may rely on the reconfiguration
request to actuate the channel activation/removal and not the
control-channel API.
So the channel reference should be decremented during reconfiguration
request, and not control_ch API.

CRs-Fixed: 389518
Change-Id: Id6ff57c6a4cad878e35004937fb08daf3b9afe7b
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
(cherry picked from commit cdce1e18ac708f976e8633f85e6d8413baa38107)

Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
msm: kgsl: Ensure correct enable sequence for 2D core clock

Calling clk_set_rate() for both AXI & 2D core clocks without putting
them in async mode causes 2D core hang. Since AXI & 2D core clocks
are in sync mode, ensure that clk_set_rate() is called only for AXI
& 2D core clock is enabled only after it is prepared.

CRs-fixed: 385393
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
(cherry picked from commit 9c4d95c79aa85364664e8e6c3fcec2c48a7b8f9d)

Change-Id: I09e8d107241c2204ff15a39fe5d1dd0dea4d22f6
Signed-off-by: Sivasri Kumar Vanka <sivasri@codeaurora.org>