Added code configuring MIPS registers CP0.Config1, CP0.Config2,
the code can be enabled by using -hwcache_conf switch.
Caution: during testing linux only boots if the cache line size is
larger than or equal 4 words (16 bytes). Also L2 values are not
detected properly for most large L2s. Linux does not list L2 cache
if MSB of SS field in Config2 is set.