write and read to regs works now, but camera doesnt stream anymore
changed qsys export pio components for proper initready and framereq. design compiles and streams flawlessly but there is a problem with mm_slave.vhd. Either mm_slave or streaming works, but not both at the same time...
excanged further pio signals in qsys. design compiles and runs, but has distortions
commented framereqout process in lvds_sync_controller.vhd again. rewrote nios functions. design compiles and streams successfully. registers are read out also. looks promising...
experimented with initregisters() in nios 2, seems as would everything work very well so far
stable version