mips64: VEX support for MIPS64 Octeon Instructions

Modeling the following Cavium Octeon instructions:

exts, exts32, cins, cins32, snei, sne, seqi, dmul, seq.

Patch by Zahid Anwar.

Bugzilla issue 322150


git-svn-id: svn://svn.valgrind.org/vex/trunk@2765 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32/mips64: additional VEX support for FCSR register.

Some mips fpu instructions are changing the value of the
fcsr register so we need to update the value of the fcsr
register in the guest state.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2766 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Unbreak the build on non-MIPS platforms.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2767 8f6e269a-dfd6-0310-a8e1-e2731360e62c
x86 front ends: tighten up decoding of MOV Ib,Eb and MOV Iv,Ev.  This
failed to check the g-register in the modrm byte, with the result that
it will mis-decode the AVX2 XABORT and XBEGIN instructions as these
instead, with obviously-bizarre consequences.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2768 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for the Intel TM "xbegin" instruction, by jumping directly
to the failure address.  Currently disabled pending finding hardware
that can actually execute xbegin, for testing purposes.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2769 8f6e269a-dfd6-0310-a8e1-e2731360e62c