macm-msm/idle-v7.S updates backported from codeaurora msm-3.4

msm: idle-v7.S: Warmboot support for NR_CPUS >= 2

The change supports save/restore of processor state during warmboot when
the number of cores is greater than 2. The current version supports two
cores only.

Change-Id: Icd23f10cde00a5dbe0abc1a76f1555f8834053a3
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
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msm: idle-v7: Power collapse Krait with caches enabled

The SCTLR[C/I] bits do not need to be cleared when entering
power collapse on Krait CPUs.

Change-Id: Ic33b227fe55a87e10aab46e6a30f44cc400ccfbb
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
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msm: idle-v7: Remove redundant cache clean

Cleaning the register save area is not necessary if we are
already cleaning the entire cache. Eliminate the redundant
cleaning operation to reduce power collapse latency.

Change-Id: I3651083f147874fd6003cfe12b07861689ca77cc
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

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msm: idle-v7 : Restore context for NR_CPUS >= 2 when PC fails

When there is a pending interrupt and the core executes WFI
instruction, the SPM would not trigger its state machine and would
bail out. The instructions after the WFI instruction will be executed.
The context calculation need to take care of getting the right context
to restore.

Change-Id: Icda4abe68503250f27b8c9b89891318beab86a7b
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
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msm: idle-v7: do not clean and invalidate after warm boot

The boot chain will already have invalidated any caches which
contain invalid data due to powering the caches on, so it is not
necessary to do that operation here. This call is also incorrect
because it is being done after caches are already enabled.

Change-Id: I1402f08712f45cb4598bcbc470b89637c1952056
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>