Added Austin's Params.scala to the chisel source.
Fixed Json import library. Ported Params.scala to Chisel 2.0.
Clean up isLit/litOf tomfoolery
fix: update scct to 0.2.1 after 0.2 was removed from maven repo
add option to build with Maven3 - thanks Rupert
Improve Mux1H QoR

The previous implementation did not take advantage of the one-hot
property of the input, resulting in a priority encoder.

I also removed some redundant constructors (leveraging Vec <: Seq).
Improve PriorityEncoderOH QoR

Exposing a higher-level priority encoder structure improves QoR for
Synopsys DC, at least.  (It also results in fewer Chisel nodes.)
Remove old "otherwise" object

This appears to be a holdover from when "when" statement priority was
inverted.  Now it only serves to create bugs.
Fix Vec.fill(0)

Vec.apply previously examined the first element of the input, which didn't
exist for Vec.fill(0).  Also, since ROM and Vec now use clone, they no
longer need to be passed a gen.
fix bug in Cpp.scala when block has zero strings
Added fake load to work with sha3
Handle incorrect bus extraction in the front-end

Things like foo(0,1) (instead of the correct foo(1,0)) result in helpful
error messages, rather than incorrect Verilog.
Params working with perl scritps
Fix bug causing invalid verilog for bit indexing
doc updates
Fix VCD compilation errors
fix memWrite inference problem and update flo backend to at least be close to correct on multiword
merge memWrite inference problem and flo backend updates
Added Params.scala, with old versions as .txt. 'sbt compile' fails for unknown reason
Merge branch 'dse' of https://github.com/ucb-bar/chisel into dse