[MIPS] Optimize opcodes to avoid bubble in pipeline.

Possible bubbles between fetch(ldr) and extract(and).
Excute subsequent instruction(s) in between the bubble by
reordering instructions

Change-Id: Ie046fd005f10ef1be08281642e69e40bab5366c1
Signed-off-by: Douglas Leung <douglas@mips.com>
[MIPS] Fixing FP registers fs0 and fs1 corruption bug.

There was an earlier patch which fixed the same problem in the
"mterp" code. This patch is for fixing the JIT template code.

For performance reasons, we don't want to use "callee saved" FP registers.
The fix is to just use temporary FP registers instead.

Change-Id: I93b75d15a9208d1a18c1b45445eb175db7d88818
Signed-off-by: Douglas Leung <douglas@mips.com>
[MIPS] Use sync instruction in dvmCompilerGenMemBarrier

Change-Id: Id647a126b0d6b1666c001a87c59a0930762778b2
Signed-off-by: Douglas Leung <douglas@mips.com>
[MIPS] Fix a problem with the FPU double alignment workaround.

This patch fixes the following cts failure:
tests.api.java.lang.reflect.MethodTest#test_invokeLjava_lang_Object$Ljava_lang_Object

Change-Id: If29c138418a3df6e195947c8e3d80f2cfd6aa9db
Signed-off-by: Douglas Leung <douglas@mips.com>
Fix a minor leak in dvmCreateInlineSubsTable

Change-Id: I1dce0e24c861903e8f5eccb23a7e2865ae8c9cec
Fix minor leaks caused by failed initialization in JNI_CreateJavaVM

Change-Id: I97e4b162fa729c97a1e71786b696f2befed56835
Fix a minor bug in dvmCreateInterpThread

Change-Id: I452ee02290bc7e0be7fefcf5755c5cd9628142dc
Remove unused compiler templates for armv7-a*

Change-Id: I68e344c2f2689347d6eeb943030b7263a55cd0bd