Zynq Hardware Managing Node with dual processor library

This branch consists the implementation of openPOWERLINK stack v2.0 on Zynq SoC running on dual processors.
ARM core of Zynq is used to run the user layer of the openPOWERLINK stack along with a demo application to demonstrate the use of API's on such platform whereas the kernel layer runs on softcore MICROBLAZE processor implemented on the FPGA part of Zynq.

The two processors use shared DDR for exchange of status/control information and data. Interrupts are used to synchronize the data exchange between the two processors.

This version is upgraded to Xilinx v14.6 ISE/SDK release to avoid additional boot loader repository since some issues were faced with v14.5.