sim/cpu: use correct PSR value when saving for SWI.

The value in the control regs might be stale.  Reconstruct it from the
cpu local flags.
sim/irq: process interrupts before instructions.

Otherwise we end up processing two instructions in the same cycle.  This
sim isn't cycle accurate so we know that we've processed all exceptions
in previous cycles.
rtl/fetch: process IRQ's correctly.

We need to latch in the start of an IRQ when we begin processing it else
we could get confused when the irq_req line goes high during the middle
of a multicycle fetch or stall - we'd end up processing the IRQ but
storing the wrong fault address and maybe worse depending on timing.
rtl/timer: implement IRQ's.
rtl/keynsham: connect timer IRQ's up to the IRQ controller.
tests/irq: fixup irq test.