add rm48x50 bsp and libcpu

We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:

    1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
    channel 5 in enabled and connected to IRQ.

    2, RTI driver is enabled and compare3 source is selected to counter1
    and the compare3 will generate tick in the period of 10ms. This
    value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.

In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
rm48x50: utilize CPS instruction and remove some useless code
rm48x50: optimize context_switch_interrupt_do

Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
rm48x50: add reg_test from FreeRTOS

The code is GPLv2 so I think we could use it for free(both free beer and
free speech).
rm48x50: fix bug in reg_test from FreeRTOS

It does not satisfy AAPCS.
rm48x50: add vRegTestTask2
rm48x50: temperately disable the VFP register test
rm48x50: optimize context_switch_interrupt_to by reuse registers

When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
rm48x50: optimize a BEQ

Use condition flag in the ORR. This could eliminate a BEQ.
rm48x50: update HALCoGen file
rm48x50: now it has console
add TI CCS support micros in rtdef.h
rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}
finsh: add CCS support
rm48x50/uart.c: fix bugs
rm48x50: add finsh support
rm48x50: move uart.c to drv_uart.c
rm48x50: small cleanup on context_ccs.asm
rm48x50: remove unused vPortTaskUsesFPU
Merge pull request #97 from heyuanjie87/ForPullRequest

For pull request