grouper update defconfigs:

  Use LZMA kernel compression
  Pass the -O2 flag instead of -Os
cpufreq interactive governor: Unify attribute store functions

Change our added attributes' store functions to Google style

Change-Id: I5dc641112085698918e87b52378fe3a5bfe44360
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/84452
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
cpufreq: interface for setting governor for a cpu

This implementation sets governor for a cpu using existing
cpufreq interfaces.

bug 871958

Change-Id: Ic4e7e2a2b0babaf1829b559b5db211666d449b86
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/97939
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
cpufreq: fix memory leak with sysfs when stats table are freed

bug 1001593

Change-Id: Ib1bf525e5c4c7ed633073a3d0b990703840dad77
Signed-off-by: Shaoming Feng <shaomingf@nvidia.com>
Reviewed-on: http://git-master/r/112025
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
cpufreq: protect cpufreq_stats_free_table with spinlock

Prevents crash on cpufreq_stat_notifier_trans when cpufreq_stats_table
has been freed due to a core being hotplugged out.

Bug 948348

Change-Id: I2640a9a23c9a79cad8c76bfefd243a07162d2004
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
(cherry picked from commit 03070a4b0b8eb74825c99c6bbfb108ddb36a041c)
Reviewed-on: http://git-master/r/114248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
cpufreq: interactive: Add Uevent Signal on Gov Start

Sends kobject_uevent signal back to userspace to signal that
the cpufreq governor has been set to interactive

Bug 1039141

Change-Id: I699e9d5834a1874b36c675764c080112ccba0f9f
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/131224
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
cpufreq: Protected access of policy attribute

It takes read RW semaphore to access policy governor

bug 997731

Change-Id: Ibdc3dd54cf6076c0fef4bc58f144e4bcb4631d76
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/107079
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: clock: Apply shared bus ceiling always

Apply shared bus ceiling regardless of whether Tegra3 SHARED_CEILING
user is enabled or disabled. Thus, we no longer need to enable ceiling
user - and the bus itself via child-parent relations - to cap the bus
rate.

Bug 954896

Change-Id: I7f96f03f05fd39334c9ee977cd1ac18d86a1fc0d
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 07b1a707aa14dcab37f095a3bb78af79a54c399b)
Reviewed-on: http://git-master/r/95739
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Arm: tegra: p1852: Avp clock frequency to 334

changed the max avp clock from 378MHz to 334MHz as per new POR changes

Bug 883565

Change-Id: I4e9dda0288f3f85c8b1705971bb8f389127cff28
Reviewed-on: http://git-master/r/97279
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/100870
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
arm: tegra: resolve compilation time warnings

Bug 949219

Change-Id: I91a67d30869e9800c483f112d58b9f76e2dbe361
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/103534
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Re-factor CPU alternative dvfs

Removed alternative frequencies table from dvfs structure, and
replaced it with table pointer to facilitate future support for
multiple alternative tables. Actually supported alternative dvfs
table (Tegra3 CPU cold zone table) is not changed.

Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104882
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Alter CPU dvfs on EDP events

Extended EDP processing of cpu up/down events with calls to alter CPU
dvfs table. This is in addition to already supported changing of CPU
dvfs on EDP thermal event. For now, added calls do not actually alter
the table.

Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104883
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Separate Tegra3 single core dvfs table

On Tegra3 added mechanism to alter dvfs table between single and
multiple CPU cores. This mechanism is dormant since no single-core
table is available yet.

Change-Id: I63bd513bd5fd7347f64c88f46974cf7fac55c419
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/105508
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Update Tegra3 display subsystem dvfs tables

Updated 0.95V entries in Tegra3 dvfs tables for display and dsi
with recent characterization results. Removed hdmi and crt dvfs
since characterization allows running these modules at max rate
in the entire supported voltage range.

Bug 817679
Bug 841336

Change-Id: I28651a692e30a20536613460ea0e45155a530af7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107778
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: Tegra: cardhu: Let emc to 450MHz on T33+ at 1V

Change dvfs table to allow emc to hit 450MHz at 1V VDD_CORE.
Line in emc table is also used for T30/T30s but because
those can't reach 1350mV they should never use a 450MHz
bct and therefore jump from 400@1V to 800@1.2V as before.

Bug 973238

Change-Id: I4f1f96c959658e6f9aeca8841c2bfa86fe20cfb8
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/101868
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Update Tegra3 I/O dvfs tables

Updated 0.95V entries in Tegra3 dvfs tables for nand, nor, spi, and
pwm clocks with recent characterization results. Removed usb, pcie,
and spdif dvfs since characterization allows running these interfaces
in the entire supported voltage range.

Bug 817679
Bug 841336

Change-Id: Iaaa2a3ff8b3c07915f1cb05e7b14da545428888e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107779
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: Tegra: Enable 900MHz at 1V on restricted pll_m

Allow pll_m to reach 900MHz at 1V on T30, T33, T37
rev A02+ SKUs.

Bug 891320

Change-Id: Idbfb10014ae2a1d06abc3bc1d0bed59c583fac98
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/103453
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Fix error checking of voltage

Fix error checking of predicted voltage. Also get rid of
maybe-uninitialized warning when using 4.6 toolchain.

Bug 949219
Bug 999222

Change-Id: I47553aba5a93c91bdd93cbf75081d69f92aec4dd
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/108899
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Update Tegra3 dsi dvfs tables

Updated entries in Tegra3 dsi dvfs tables with recent characterization results.

Bug 985671.
Bug 1006163.

Change-Id: Ife87f3ccfd9d6147d4aa5b57c1a5750bbabc7e6b
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/112805
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Zu <pzu@nvidia.com>
ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tables

Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum
clock limits based on recent characterization results.

Bug 817679
Bug 841336

Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107780
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>