Fix an ambiguity between elements of arrays and nodes in buses. To the parser, they look exactly the same, so we have to check in the symbol table to figure out what it is.
Ensure that variables and arrays used in events get added to the instance or model if their values need to persist between simulation steps.
Remove the semicolon at the end of assignment objects because it breaks for loops.
Writing '<' in the Verilog-A code would get translated into '<=', so let's fix that.
Make array indexes and ranges take expressions rather than integers.
Fix scope for variables used in events.