i965: Go back to using the kernel SOL reset feature.

It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell,
and regressed essentially all the transform feedback Piglit tests.

This morally reverts eaa6fbe6d54dc99efac4ab8e800edef65ce8220d.  However,
the code is still simpler than it was.  On BeginTransformFeedback, we
simply flush the batch and set the SOL reset flag so that the next batch
will start with zeroed offsets.  There's still no software counting.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
r600g/compute: Use common transfer_{map,unmap} functions for kernel inputs

Reviewed-by: Marek Olšák <maraeo@gmail.com>
r600g/compute: Use common transfer_{map,unmap} functions for global resources

Reviewed-by: Marek Olšák <maraeo@gmail.com>
r600g/sb: fix buffer overflow in sb_ostream

Fixes segfault during bytecode dump with bfgminer kernel

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: fix gpr array handling for compute shaders

Fixes segfault with bfgminer and R600_DEBUG=sbcl.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: relax register allocation for compute shaders

We have to assume that all GPRs in compute shader can be indirectly
addressed because LLVM backend doesn't provide any indirect array info.
That's why for compute shaders GPR array is created that covers all used
GPRs (0..r600_bytecode::ngpr-1), but this seriously restricts register
allocation in sb.

This patch checks for actual use of indirect access in the shader and
if it's not used then GPR array is not created, so that regalloc is not
unnecessarily restricted.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: relax some restrictions for FETCH instructions

This allows GVN rewrite pass to propagate non-const (register)
values to FETCH source operands, helping to eliminate unnecessary
copies in some cases.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: fix incorrect assert

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
st/glx/xlib: assorted whitespace, comment fixes
st/mesa: add switch cases for new IR enums to silence warnings
st/glx: add null ctx check in glXDestroyContext()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
xlib: add null ctx check in glXDestroyContext()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934
NOTE: This is a candidate for the stable branches.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
r600g/sb: fix handling of preloaded inputs for compute shaders

For compute shaders we need to let the backend know that
GPRs 0 and 1 are preloaded with some compute-specific input
values, otherwise any use of these regs without previous
definition is considered as undefined value and usually
is simply replaced with 0.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: fix scheduling of PRED_SET instructions

PRED_SET instructions that update exec mask should be scheduled immediately
prior to the "if-then-else" block, because any instruction that is
inserted after alu clause with PRED_SET and before conditional block is
also conditionally executed by hw (exec mask is already updated at that
moment).

Propbably it's better to make PRED_SET a part of conditional
"if-then-else" block in the IR to handle this more cleanly,
but for now this temporary solution should prevent the problem.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: fix peephole optimization for PRED_SETE

Fixes incorrect condition that prevented optimization for
PRED_SETE/PRED_SETE_INT.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
r600g/sb: improve handling of KILL instructions

This patch improves handling of unconditional KILL instructions inside
the conditional blocks, uncovering more opportunities for if-conversion.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
tgsi: add buffer texture to tgsi_util_get_texture_coord_dim()

TGSI_TEXTURE_BUFFER is one-dimensional.  Assert that exec_tex() is never
called with TGSI_TEXTURE_BUFFER.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
ilo: add support for texture buffer objects

Take care of sampler views that have buffers as the underlying resources.
Update caps related to TBOs.
ilo: advertise supports for pure integer formats

For pure integer formats, no filtering nor blending is needed.
ilo: add support for TBOs on GEN6

This hunk was missing in the last commit.