ARC: Ensure coherency between caches and memory

This commit does several things to ensure that cache and memory are in
coherent state as far as both target core and debugger are
concerned. Changes are:

* Make call to cache invalidation cheap, now it performs JTAG operations
  only when caches haven't been invalidated since core had been halted;

* Add function to flush data cache. It uses the same algorithm as
  invalidation and is cheap to call;

* Add command "arc has-dcache <bool>". If value is true, then D$ will be
  flushed before memory reads. Default is true.

* Each arc_mem_(read|write)_block invocation will trigger cache flush
  before doing anything, then in will invalidate caches.

* Do not invalidate caches after setting/resetting breakpoints. This is
  now handled in memory ops. Previous way didn't handled situation when
  user changes memory directly instead of just setting/resetting
  breakpoints.

Without this patch there is no guarantee that debugger will read values
written to memory by the core, because they might still be unflushed.
This was causing weird behaviour, because after resume even core itself
was reading some invalid values from memory instead of the right ones.

Reported-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Signed-off-by: Anton Kolesov <anton.kolesov@synopsys.com>
ARC: Add RHEL build instructions

Signed-off-by: Anton Kolesov <anton.kolesov@synopsys.com>
Support big endian EM Starter Kit

Add a script for big-endian EM Starter Kit.

Signed-off-by: Anton Kolesov <anton.kolesov@synopsys.com>
ARC: Reset caches states variables after step

Older commit that introduced flushing of D$ and more complex logic for
invalidating I$/D$ wasn't handling single steps, it worked only when
user was "continuing". To fix this and avoid code repetition separate
function for reseting internal variables is introduced, and this
functions is called when target enter debug state.

Signed-off-by: Anton Kolesov <anton.kolesov@synopsys.com>